mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 164

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Controller – Digital (BDLC–D)
Advance Information
CRC Error
Symbol Error
Framing Error
Bus Fault
immediately will cease transmitting. The error condition is reflected in
the BSVR (see
set, a CPU interrupt request from the BDLC is generated.
A cyclical redundancy check (CRC) error is detected when the data
bytes and CRC byte of a received message are processed and the
CRC calculation result is not equal. The CRC code will detect any
single and 2-bit errors, as well as all 8-bit burst errors and almost all
other types of errors. The CRC error flag (in BSVR) is set when a CRC
error is detected. See
A symbol error is detected when an abnormal (invalid) symbol is
detected in a message being received from the J1850 bus. The
invalid symbol is set when a symbol error is detected. See
BDLC State Vector
A framing error is detected if an EOD or EOF symbol is detected on a
non-byte boundary from the J1850 bus. A framing error also is
detected if the BDLC is transmitting the EOD and instead receives an
active symbol. The symbol invalid, or the out-of-range flag, is set
when a framing error is detected. See
Register.
If a bus fault occurs, the response of the BDLC will depend upon the
type of bus fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to
a passive state before it will attempt to transmit a message. As long
as the short remains, the BDLC will never attempt to transmit a
message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin
to transmit the message, and then detect a transmission error (in
BSVR), since the short to ground would not allow the bus to be driven
to the active (dominant) SOF state. The BDLC will abort that
transmission and wait for the next CPU command to transmit.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller – Digital (BDLC–D)
Go to: www.freescale.com
Table
Register.
14-5). If the interrupt enable bit (IE in BCR1) is
14.7.4 BDLC State Vector
14.7.4 BDLC State Vector
MC68HC705V12
Register.
14.7.4
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Rev. 3.0