mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 169

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

14.7.2 BDLC Control Register 1
MC68HC705V12
—
Rev. 3.0
Address:
This register is used to configure and control the BDLC.
IMSG — Ignore Message Bit
CLKS — Clock Bit
Reset:
Read:
Write:
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
For J1850 bus communications to take place, the nominal BDLC
operating frequency (f
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU
system clock is divided to form the MUX interface clock (f
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
1 = Disable receiver. When set, all BDLC interrupt requests will be
0 = Enable receiver. This bit is cleared automatically by the
1 = Binary frequency (1.048576 MHz) selected for f
0 = Integer frequency (1 MHz) selected for f
$003A
IMSG
Bit 7
masked (except $20 in BSVR) and the status bits will be held
in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
R
1
Figure 14-17. BDLC Control Register 1 (BCR1)
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= Reserved
CLKS
6
1
BDLC
R1
5
1
) must always be 1.048576 MHz or 1 MHz.
R0
Byte Data Link Controller – Digital (BDLC–D)
4
0
R
3
0
0
BDLC
R
2
0
0
BDLC CPU Interface
Advance Information
BDLC
IE
1
0
BDLC
) which
WCM
Bit 0
0