mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 181

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

14.7.5 BDLC Data Register
MC68HC705V12
—
Rev. 3.0
Address:
This register is used to pass the data to be transmitted to the J1850 bus
from the CPU to the BDLC. It is also used to pass data received from the
J1850 bus to the CPU. Each data byte (after the first one) should be
written only after a Tx data register empty (TDRE) state is indicated in
the BSVR.
Data read from this register will be the last data byte received from the
J1850 bus. This received data should only be read after an Rx data
register full (RDRF) interrupt has occurred. See
Vector
The BDR is double buffered via a transmit shadow register and a receive
shadow register. After the byte in the transmit shift register has been
transmitted, the byte currently stored in the transmit shadow register is
loaded into the transmit shift register. Once the transmit shift register has
shifted the first bit out, the TDRE flag is set, and the shadow register is
ready to accept the next data byte. The receive shadow register works
similarly. Once a complete byte has been received, the receive shift
register stores the newly received byte into the receive shadow register.
The RDRF flag is set to indicate that a new byte of data has been
received. The programmer has one BDLC byte reception time to read
the shadow register and clear the RDRF flag before the shadow register
is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop
loading data into the BDR. This will cause a transmitter underrun error
and the BDLC automatically will disable the transmitter on the next
non-byte boundary. This means that the earliest a transmission can be
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
Register.
$003D
Bit 7
BD7
Go to: www.freescale.com
Figure 14-21. BDLC Data Register (BDR)
BD6
6
BD5
5
Indeterminate after reset
BD4
Byte Data Link Controller – Digital (BDLC–D)
4
BD3
3
14.7.4 BDLC State
BD2
2
BDLC CPU Interface
Advance Information
BD1
1
Bit 0
BD0