mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 202
mc68hc705v12
Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC705V12.pdf
(248 pages)
- Current page: 202 of 248
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Gauge Drivers
15.7.2 Scan Status and Control Register
Advance Information
Address:
Although the CDR and CMRs can be written at any time, the user may
want to write the CDR and CMRs at a particular time in the scanning
sequence. Some of the bits in the SSCR give the user the information
needed to synchronize the writes to the CDR and CMRs with the coil
sequencer.
In addition to the sychronization bits, this register also contains a bit that
affects the type of scanning that will take place (automatic or manual)
and a bit to initiate a scan cycle manually when using manual mode.
SYNIE — Synchronize Interrupt Enable Bit
SYNF — Synchronize Flag Bit
Reset:
Read:
Write:
6. Wait for sample and hold to settle.
7. Go back to step 1.
When this bit is set, an interrupt signal will be sent to the CPU when
the SYNF bit is set. The I bit in the CPU condition code register must
be cleared in order for the interrupt to be recognized by the CPU. The
interrupt vector assigned to the gauge module is shown in
Table
This bit is a read-only status bit and indicates that the coil sequencer
has begun to service coil 11 (minor D). At this point in the scanning
cycle, it is safe to write any of the CMRs or CDRs without affecting the
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 15-13. Scan Status and Control Register (SSCR)
1 = Interrupt is enabled.
0 = Interrupt is disabled.
SYNIE
$0021
BIt 7
15-2.
0
Go to: www.freescale.com
= Unimplemented
SYNF
Gauge Drivers
6
0
SYNR
5
0
0
R
4
0
GCS1
R
3
0
= Reserved
MC68HC705V12
GCS0
2
0
SCNS
1
0
—
Rev. 3.0
AUTOS
Bit 0
0
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