mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 63

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

MC68HC705V12
NOTE:
—
Rev. 3.0
The IPCE mask bit must be set prior to entering stop or wait modes if port
IRQ interrupts are to be enabled.
IRQF — IRQ Interrupt Request Bit
IPCF — Port C IRQ Interrupt Request Bit
IRQA — IRQ Interrupt Acknowledge Bit
cleared, the IPCF flag bit will not generate an interrupt sequence.
Reset clears the IPCE enable bit, thereby disabling port C IRQ
interrupts. In addition, reset also sets the I bit, which masks all
interrupt sources. Execution of the STOP or WAIT instructions does
not affect the IPCE bit.
The IRQF flag bit indicates that an IRQ request is pending. Writing to
the IRQF flag bit will have no effect on it. The IRQF flag bit is cleared
when the IRQ vector is fetched prior to the service routine being
entered. The IRQF flag bit also can be cleared by writing a logic one
to the IRQA acknowledge bit to clear the IRQ latch. In this way, any
additional IRQF flag bit that is set while in the service routine can be
ignored by clearing the IRQF flag bit before exiting the service routine.
If the additional IRQF flag bit is not cleared in the IRQ service routine
and the IRQE enable bit remains set, the CPU will re-enter the IRQ
interrupt sequence continuously until either the IRQF flag bit or the
IRQE enable bit is clear. This flag can be set only when the IRQE
enable is set. The IRQ latch is cleared by reset.
The IPCF flag bit indicates that a port C IRQ request is pending.
Writing to the IPCF flag bit will have no effect on it. The IPCF flag bit
must be cleared by writing a logic 1 to the IRQA acknowledge bit. If
the IPCF bit is not cleared via IRQA, the CPU will re-enter the IRQ
interrupt sequence continuously until either the IPCF flag bit or the
IPCE enable bit is clear. This bit is operational regardless of the state
of the IPCE bit. The IPCF bit is cleared by reset.
The IRQA acknowledge bit clears an IRQ interrupt by clearing the
IRQF and IPCF bits. This is achieved by writing a logic 1 to the IRQA
acknowledge bit. Writing a logic 0 to the IRQA acknowledge bit will
have no effect on the any of the IRQ bits. If either the IRQF or IPCF
bit is not cleared within the IRQ service routine, then the CPU will
re-enter the IRQ interrupt sequence continuously until the IRQ flag
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Interrupts
External Interrupt (IRQ)
Advance Information
Interrupts