mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 73

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

5.4.2.5 COP Register
5.4.3 Illegal Address Reset
5.4.4 Disabled STOP Instruction Reset
5.4.5 Low-Voltage Reset (LVR)
MC68HC705V12
—
Rev. 3.0
Address:
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in
this location will return whatever user data has been programmed at this
location. Writing a 0 to the COPR bit in this location will clear the COP
watchdog timer.
An illegal address reset is generated when the CPU attempts to fetch an
instruction from either unimplemented address space ($01C0 to $023F
and $0340 to $0CFF) or I/O address space ($0000 to $003F).
The illegal address reset will activate the internal pulldown device
connected to the RESET pin.
When the mask option is selected to disable the STOP instruction,
execution of a STOP instruction results in an internal reset. This
activates the internal pulldown device connected to the RESET pin.
The internal LVR is generated when V
V
rises above V
Read:
Write:
Reset
LVRI,
Freescale Semiconductor, Inc.
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and will be released following a POR delay starting when V
$3FF0
Bit 7
X
X
Figure 5-3. COP Watchdog Timer Location
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LVRR
= Unimplemented
X
X
6
. The LVR threshold is tested to be above the
Resets
X
X
5
X
X
4
DD
falls below the LVR threshold,
X
X
3
Figure
2
X
X
Advance Information
5-3. Reading
Internal Resets
1
X
X
COPR
Resets
Bit 0
DD
X
X