mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 83

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
7.4 Port B
7.4.1 Port B Data Register
MC68HC705V12
INTERNAL HC05
DATA BUS
WRITE $0005
WRITE $0001
READ $0005
READ $0001
Rev. 3.0
RESET
(RST)
Port B is an 8-bit bidirectional port. Each port B pin is controlled by the
corresponding bits in a data direction register and a data register as
shown in
in
shared with 16-bit timer functions. See
description. PB0–PB3 are shared with the SPI as shown in
Serial Peripheral Interface
located at address $0001. The port B data direction register (DDRB) is
located at address $0005. Reset clears the DDRB register. The port B
data register is unaffected by reset.
Each port B I/O pin has a corresponding bit in the port B data register.
When a port B pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port B pin is programmed as an input, any read of the port B data
register will return the logic state of the corresponding I/O pin. The port
B data register is unaffected by reset.
Section 11. Pulse Width Modulators (PWMs)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-2. Port B I/O Circuitry
DATA DIRECTION
Figure
REGISTER BIT
REGISTER BIT
DATA
Go to: www.freescale.com
Parallel Input/Output (I/O)
7-2. PB5 and PB4 are shared with the PWMs as shown
(SPI). The port B data register (PORTB) is
SPI MUX LOGIC
16-BIT TIMER,
PMWs, AND
Section 9. 16-Bit Timer
OUTPUT
and PB7 and PB6 are
Parallel Input/Output (I/O)
Advance Information
Section 10.
for timer
PIN
I/O
Port B

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