mpc850de Freescale Semiconductor, Inc, mpc850de Datasheet - Page 38
mpc850de
Manufacturer Part Number
mpc850de
Description
Mpc850 Rev. A/b/c Communications Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC850DE.pdf
(68 pages)
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Layout Practices
38
Num
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO data invalid
TCK low to TDO high impedance
TRST assert time
TRST setup time to TCK low
TCK falling edge to output valid
TCK falling edge to output valid out of high
impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
Characteristic
Figure 35. JTAG Test Access Port Timing Diagram
MPC850 (Rev. A/B/C) Hardware Specifications
Figure 34. JTAG Test Clock Input Timing
Table 12. JTAG Timing (continued)
100.00
25.00
40.00
50.00
50.00
0.00
Min
—
—
—
—
—
50 MHz
27.00
20.00
50.00
50.00
50.00
Max
—
—
—
—
—
—
100.00
25.00
40.00
50.00
50.00
0.00
Min
—
—
—
—
—
66MHz
27.00
20.00
50.00
50.00
50.00
Max
—
—
—
—
—
—
100.00
25.00
40.00
50.00
50.00
0.00
Min
—
—
—
—
—
80 MHz
MOTOROLA
27.00
20.00
50.00
50.00
50.00
Max
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns