gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 83
gc80c510
Manufacturer Part Number
gc80c510
Description
Eprom/rom 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C510.pdf
(211 pages)
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MiDAS1.1 Family
machine cycles to complete the IE, IP, EIE, EIP, IPH or EXIF access, 4 machine cycles to complete the
instruction and 4 machine cycles to complete the hardware LCALL to the interrupt vector location.
Thus in a single-interrupt system, the interrupt response time will always be more than 5 machine
cycles and not more than 11 machine cycles. The maximum latency of 11 machine cycle is 44 clock
cycles. Note that in the standard 80C52, the maximum latency is 8 machine cycles which equals 96
clock cycles. This is more than 50% reduction in terms of clock periods.
Page 83 of 211
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