dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 53

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

15 0 Switching Characteristics
Note 1 Cycles T1 T2 T3 and T4 are only issued for the first transfer in a burst when 32-bit mode has been selected
Note 2 The rate of bus clock must be high enough to support transfers to from the FIFO at a rate greater than the serial network transfers from to the FIFO
Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention
Symbol
bcyc
bch
bcl
bcash
bcasl
aswo
bcadv
bcadz
ads
adh
Bus Clock Cycle Time (Note 2)
Bus Clock High Time
Bus Clock Low Time
Bus Clock to Address Strobe High
Bus Clock to Address Strobe Low
Address Strobe Width Out
Bus Clock to Address Valid
Bus Clock to Address TRI-STATE (Note 3)
Address Setup to ADS0 1 Low
Address Hold from ADS0 1 Low
Parameter
DMA Address Generation
AC Specs DP83901A Note All Timing is Preliminary (Continued)
53
bch
bcl
Min
bch
50
20
20
15
b
b
15
5
Max
125
45
34
44
55
TL F 10469 – 37
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns