dp83932c-20 National Semiconductor Corporation, dp83932c-20 Datasheet - Page 86
dp83932c-20
Manufacturer Part Number
dp83932c-20
Description
Mhz Sonictm Systems-oriented Network Interface Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83932C-20.pdf
(98 pages)
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Number
T41
T41a
T42
7 0 AC and DC Specifications
BUS RETRY
Note 1 Depending upon the mode the SONIC will assert and deassert HOLD from the rising or falling edge of BSCK
Note 2 Unless Latched Bus Retry mode is set (LBR in the Data Configuration Register Section 4 3 2) BRT must remain asserted until after the Th state If
Latched Bus Retry mode is used BRT does not need to satisfy T42
Note 3 T41 is for synchronous bus retry and T41a is for asynchronous bus retry (see Section 4 3 2 bit 15 Extended Bus Mode) Since T41a is an asynchronous
setup time it is not necessary to meet it but doing so will guarantee that the bus exception occurs in the current memory transfer not the next
Bus Retry Synchronous Setup Time to BSCK
(Note 3)
Bus Retry Asynchronous
Setup Time to BSCK (Note 3)
Bus Retry Hold Time from BSCK (Note 2)
Parameter
(Continued)
86
Min
5
6
7
20 MHz
Max
Min
4
5
6
25 MHz
Max
Min
3
4
5
33 MHz
Max
TL F 10492 – 69
Units
ns
ns
ns
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