dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 67

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

15:8
1:0
Bit
14.2.8 CD Test and BIST Extensions Register (CDCTRL1)
This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the
packet BIST function.
7
6
5
4
3
2
BIST_ERROR_COUNT
PATT_GAP_10M
CDPATTSEL[1:0]
MDIO_PULL_EN
MII_CLOCK_EN
CDPATTEN_10
RESERVED
BIST_CONT
Bit Name
TABLE 34. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B
0000 0000, RO
Default
00, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
BIST ERROR Counter:
Counts number of errored data nibbles during Packet BIST. This value
will reset when Packet BIST is restarted. The counter sticks when it
reaches its maximum count of FFh.
RESERVED: Must be 0.
Enables MII Clocks TX_CLK and RX_CLK independent of MAC
interface mode selected; for example, normally TX_CLK and RX_CLK
are disabled in RMII Slave mode.
1 = Enable TX_CLK and RX_CLK
0 = Default operation
Packet BIST Continuous Mode:
Allows continuous pseudorandom data transmission without any break
in transmission. This can be used for transmit VOD testing. This is used
in conjunction with the BIST controls in the PHYCR Register (19h). For
10 Mb operation, jabber function must be disabled, bit 0 of the
10BTSCR (1Ah), JABBER_DIS = 1.
CD Pattern Enable for 10 Mb:
1 = Enabled.
0 = Disabled.
Enable Internal MDIO Pullup:
1 = Internal MDIO pullup enabled
0 = Internal MDIO pullup disabled
This bit is only reset on hard reset. This bit should not be set in systems
that share the management interfaces among several ASICs.
Defines gap between data or NLP test sequences:
1 = 15 µs.
0 = 10 µs.
CD Pattern Select[1:0]:
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence.
01 = Data, EOP1 sequence.
10 = NLPs.
11 = Constant Manchester 1s (10 MHz sine wave) for harmonic
distortion testing.
67
Description
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