dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 79
dp83630sqx
Manufacturer Part Number
dp83630sqx
Description
Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83630SQX.pdf
(126 pages)
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15:11
Bit
9:2
10
14.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2
This register contains additional controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for
programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the
MISR. Monitor control and status are available in this register, while the LQDR register controls read/write access to threshold
values and current parameter values. Reading of LQMR2 register clears its warning bits but does NOT re-arm the interrupt gen-
eration; LQMR must be read to re-arm interrupt generation. In addition, this register provides a mechanism for allowing automatic
reset of the 100 Mb link based on the Link Quality Monitor variance status.
1
0
RESTART_ON_VAR
VAR_HI_WARN
RESERVED
RESERVED
RESERVED
Bit Name
TABLE 49. Link Quality Monitor Register 2 (LQMR2), address 0x1F
00 0000 00, RO
0000 0, RO
0, RO/COR
Default
0, RW
0, RO
Reserved: Writes ignored, Read as 0
Restart on Variance Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Offset Threshold violation. If the SD_Option bit, PCSR[8], is set to 0,
the threshold violation will also result in a drop in Link status.
Reserved: Writes ignored, Read as 0
Variance High Warning:
This bit indicates the Variance High Threshold was exceeded. This register bit will
be cleared on read.
Reserved: Writes ignored, Read as 0
79
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