dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 181

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

6 0 Reference Section
quent data memory read operations expand to 4 T-states
with an extra one-half T-state between the falling edge of
ALE and the falling edge of READ This eliminates bus con-
tention on data memory read operations After a BCP reset
or when a zero is written to this bit the DP8344B data mem-
ory read operations operate in 3 T-states as in the
DP8344A in which this bit was unused (See Section 2 2 2
for more information )
6 6 2 2 A AD Reset State
After a BCP reset the index registers and the A and AD
buses will be zero In the DP8344A their states were unde-
fined after a reset
6 6 2 3 RIC
Each time instruction memory is selected via RIC 1 0
(i e
write) of instruction memory by a remote processor will al-
ways return (or update) the low order 8 bits of the 16 bit
instruction location pointed to by the program counter In
the DP8344A setting RIC had no affect on which instruc-
tion memory byte would next be fetched and an algorithm
had to be developed to determine this (See Section 4 1 2
for more information )
6 6 2 4 Transceiver
When the Transceiver is reset DATA-OUT now goes into a
state equal to TIN
transitions on DATA-OUT and DATA-DLY with TX-ACT
(See Section 3 2 for more information
6 7 REPORT BUGS
6 7 1 History
The DP8344 Data Sheet Reference
10 29 87 (rev 3 6) listed a total of 13 bugs All these bugs
were corrected in the DP8344A released to production April
1989 Subsequent to this date an additional bug has been
reported This bug is present in all versions of the BCP
DP8344 DP8344A and DP8344B
For additional information regarding differences in function-
ality between the DP8344B and DP8344A see Section 6 6
6 7 2 LJMP LCALL Address Decode
The LJMP and LCALL instructions to the address range
Af00
tional and unconditional LCALL or LJMP instructions to this
address range will not decode as LCALL or LJMP instruc-
tions Instead the address field will be incorrectly decoded
as the instruction Thus a LJMP or LCALL to an instruction
in the address range AF00
as a RETF instruction
Example the instruction
Note that LJMP and LCALL to all other addresses work cor-
rectly
The LJMP or LCALL instruction should therefore not be
used to transfer program control to an instruction in the
range AF00
6 7 2 1 Suggested Work-around
The simplest work-around is not to place any code neces-
sary for system operation in the affected address range
4TR in ACR
h
RIC is set to XXXX XX01 binary) the next read (or
through AF7F
will be decoded as
which is
h
to AF7F
When a one is written to this bit all subse-
h
Z
h
do not function correctly Both condi-
ATA which eliminates coincident
h
through AF7F
LJMP AF00
AF00
RETF 000
(Continued)
h
will be decoded
first published
00
181
This can be accomplished by creating a section of ‘‘filler’’
code that will occupy the instruction address range AF00
to AF7F
be as follows
FILLER
The JMP $ instruction causes an infinite loop at that instruc-
tion Thus one would be able to determine if the program
inadvertently entered the ‘‘filler’’ section of code The re-
peat 128 instruction causes the section to occupy 128 bytes
of instruction memory which is the size of the affected ad-
dress range
Next by using the Linker in the DP8344 BCP Assembler
System one can specify that this ‘‘filler’’ section of code
must occupy instruction memory starting at address AF00
by using the -L option For example the following com-
mands can be entered at the DOS command line to invoke
the Assembler and Linker (this assumes that the ‘‘filler’’
section is located in the file FILLER BCP)
This will prevent any other section of code from occupying
the range which the ‘‘filler’’ section of code is located in
Hence one would not have to be concerned about using
labels to specify the address in LJMP and LCALL instruc-
tion
6 8 GLOSSARY
3270 An IBM communication protocol originally devel-
oped for the 370 class mainframe that implements a star
topology using a single coax cable per slave device In this
master-slave protocol all communication is initiated by the
controller (master) and responses are returned by the ter-
minal or other attached device (slave) The data is transmit-
ted using biphase encoding at a bit rate of 2 3587 MHz
3299 A communications protocol that is the 3270 proto-
col with an eight bit address frame added to the beginning
of each controller transmission between the start se-
quence and the first coax word Currently IBM only uses
three bits of the address field which allows up to eight devic-
es to communicate with the controller through a multiplex-
er
5250 An IBM communications protocol originally devel-
oped for the Series 3 that became widely used on the Sys-
tem 34 36 38 family of minicomputers and currently the
AS 400 It uses a multidrop bus topology on twin-ax cable
This protocol is a master-slave type The data is transmitted
using bi-phase encoding at a bit rate of 1 MHz
accumulator The implied source register of one operand
for some arithmetic operations In the BCP R8 in the cur-
rently enabled bank acts as the accumulator
ALU The Arithmetic Logic Unit a component of the CPU
that performs all arithmetic (addition and subtraction) logi-
cal (AND OR XOR compare bit test and complement)
rotational and shifting operations
ALU flags Bits that indicate the result of certain ALU func-
tions
NBCPASM FILLER BCP
NLINK -LFILLER4AF00 FILLR BCO
h
JMP $
SECT X
REPEAT 128
ENDR
END
As an example the ‘‘filler’’ section of code could
instruction 128 times
Start of ‘‘filler’’ code section
Repeat the following
Jump to self
End of repeat block
h
h