palce20ra10 Lattice Semiconductor Corp., palce20ra10 Datasheet
palce20ra10
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palce20ra10 Summary of contents
Page 1
... Registered or combinatorial outputs Programmable polarity Programmable replacement for high-speed CMOS or TTL logic GENERAL DESCRIPTION The PALCE20RA10 is an advanced PAL device built with low-power, high-speed, CMOS technology. The PALCE20RA10 offers asyn- chronous clocking for each of the ten flip-flops in the de- vice ...
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... PIN DESIGNATIONS GND = Ground I = Input I/O = Input/Output Connect OE = Output Enable PL = Preload V = Supply Voltage CC PLCC JEDEC PALCE20RA10 Family 15434H-3 2-185 ...
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... Valid Combinations lists configurations planned JC supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE20RA10H-7/10/15/20 (Com’l, Ind) I OPERATING CONDITIONS C = Commercial ( + Industrial (– +85 C) PACKAGE TYPE ...
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... Commercial and Industrial Products FUNCTIONAL DESCRIPTION The PALCE20RA10 has ten dedicated input lines and ten programmable I/O macrocells. The Registered Asynchronous (RA) macrocell is shown in Figure 1. PL serves as global register preload and OE serves as global output enable. Programmable output polarity is available to provide user-programmable output polarity for each individual macrocell ...
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... The state of combinatorial outputs will be a function of the logic. Details on power-up reset can be found on page 16. Quality and Testability The PALCE20RA10 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and ...
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... PALCE20RA10 Family (28 (27 (26) ...
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... Outputs Open mA Max, (Note 4) OUT Outputs Open mA Max, (Note 4) OUT CC and I (or I and OZL IH OZH PALCE20RA10H-7/10/15/20 (Com’l, Ind + +4. +5. – +5.5 V Min Max Unit 2.4 V 0.4 V 2 – ...
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... 2.0 V OUT -7 Min (3) Max 7.5 2.5 7 100 S CO 1/( 125 7.5 7 PALCE20RA10H-7/10/15/20 (Com’l, Ind) Typ MHz 8 -10 -15 -20 Min Min Min (3) Max (3) Max (3) Max ...
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... Input Asserting Asynchronous V T Reset V T Registered Output t APR V T Clock 15434H- Clock Width 0.5V Output 0.5V 15434H-13 PALCE20RA10 Family Registered Output t ARW Asynchronous Reset 15434G-12 t PXZ - Output Disable/Enable V ...
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... R 1 Output Commercial and Industrial All except H-20 300 5 pF H-20: 560 PALCE20RA10 Family OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point ...
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... By utilizing 50% of the device, a midpoint is defined for From this midpoint, a designer may scale the I CC graphs up or down to estimate the I CC requirements for a particular design. 2-194 Frequency (MHz) I vs. Frequency CC PALCE20RA10 Family PALCE20RA10 Family 15434H-16 50 ...
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... ENDURANCE CHARACTERISTICS The PALCE20RA10 is manufactured using our ad- vanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Symbol Parameter t Min Pattern Data Retention Time DR N Min Reprogramming Cycles Robustness The PALCE20RA10 has been designed with some unique features that make it extremely robust, even when operating in high-speed design environments ...
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... POWER-UP RESET The PALCE20RA10 has been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This fea- ture provides extra flexibility to the designer and is espe- cially valuable in simplifying state machine initialization ...