palce20ra10 Lattice Semiconductor Corp., palce20ra10 Datasheet

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palce20ra10

Manufacturer Part Number
palce20ra10
Description
24-pin Asynchronous Ee Cmos Programmable Array Logic
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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2-184
PALCE20RA10 Family
24-Pin Asynchronous EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE20RA10 is an advanced PAL device built
with
CMOS technology. The PALCE20RA10 offers asyn-
chronous clocking for each of the ten flip-flops in the de-
vice. The ten macrocells feature programmable clock,
preset, reset, and enable, and all can operate
asynchronously to other macrocells in the same device.
The PALCE20RA10 also has flip-flop bypass, allowing
any combination of registered and combinatorial
outputs.
The PALCE20RA10 utilizes the familiar sum-of-prod-
ucts (AND/OR) architecture that allows users to imple-
ment complex logic functions easily and efficiently.
Multiple levels of combinatorial logic can always be re-
duced to sum-of-products form, taking advantage of the
BLOCK DIAGRAM
Enable
Output
Low power at 100 mA I
As fast as 7.5 ns maximum propagation delay
and 100 MHz f
Individually programmable asynchronous
clock, preset, reset, and enable
Registered or combinatorial outputs
Programmable polarity
Programmable replacement for high-speed
CMOS or TTL logic
Macro
USE GAL DEVICES FOR NEW DESIGNS
low-power,
4
I/O
3
0
FINAL
Macro
4
I/O
MAX
high-speed,
3
1
(external)
Macro
CC
4
I/O
3
2
electrically-erasable
COM’L: H-7/10/15/20
Macro
4
I/O
3
3
Programmable AND Array
Macro
4
I/O
Dedicated
3
40 x 80
4
10
Inputs
I
9
Macro
– I
4
I/O
very wide input gates available in PAL devices.
The equations are programmed into the device through
floating-gate cells in the AND logic array that can be
erased electrically.
0
3
5
TTL-level register preload for testability
Extensive third-party software and programmer
support through FusionPLD partners
24-pin PDIP and 28-pin PLCC packages save
space
7.5 ns, 10 ns, and 15 ns versions utilize split
leadframes for improved performance
IND: H-7/10/15/20
Macro
4
I/O
3
6
Lattice Semiconductor
Macro
4
I/O
Publication# 15434
Issue Date: February 1996
3
7
Macro
4
I/O
3
8
Rev. H
Macro
4
I/O
Preload
Amendment /0
3
9
15434H-1
Preload

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palce20ra10 Summary of contents

Page 1

... Registered or combinatorial outputs Programmable polarity Programmable replacement for high-speed CMOS or TTL logic GENERAL DESCRIPTION The PALCE20RA10 is an advanced PAL device built with low-power, high-speed, CMOS technology. The PALCE20RA10 offers asyn- chronous clocking for each of the ten flip-flops in the de- vice ...

Page 2

... PIN DESIGNATIONS GND = Ground I = Input I/O = Input/Output Connect OE = Output Enable PL = Preload V = Supply Voltage CC PLCC JEDEC PALCE20RA10 Family 15434H-3 2-185 ...

Page 3

... Valid Combinations lists configurations planned JC supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE20RA10H-7/10/15/20 (Com’l, Ind) I OPERATING CONDITIONS C = Commercial ( + Industrial (– +85 C) PACKAGE TYPE ...

Page 4

... Commercial and Industrial Products FUNCTIONAL DESCRIPTION The PALCE20RA10 has ten dedicated input lines and ten programmable I/O macrocells. The Registered Asynchronous (RA) macrocell is shown in Figure 1. PL serves as global register preload and OE serves as global output enable. Programmable output polarity is available to provide user-programmable output polarity for each individual macrocell ...

Page 5

... The state of combinatorial outputs will be a function of the logic. Details on power-up reset can be found on page 16. Quality and Testability The PALCE20RA10 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and ...

Page 6

... PALCE20RA10 Family (28 (27 (26) ...

Page 7

... Outputs Open mA Max, (Note 4) OUT Outputs Open mA Max, (Note 4) OUT CC and I (or I and OZL IH OZH PALCE20RA10H-7/10/15/20 (Com’l, Ind + +4. +5. – +5.5 V Min Max Unit 2.4 V 0.4 V 2 – ...

Page 8

... 2.0 V OUT -7 Min (3) Max 7.5 2.5 7 100 S CO 1/( 125 7.5 7 PALCE20RA10H-7/10/15/20 (Com’l, Ind) Typ MHz 8 -10 -15 -20 Min Min Min (3) Max (3) Max (3) Max ...

Page 9

... Input Asserting Asynchronous V T Reset V T Registered Output t APR V T Clock 15434H- Clock Width 0.5V Output 0.5V 15434H-13 PALCE20RA10 Family Registered Output t ARW Asynchronous Reset 15434G-12 t PXZ - Output Disable/Enable V ...

Page 10

... R 1 Output Commercial and Industrial All except H-20 300 5 pF H-20: 560 PALCE20RA10 Family OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point ...

Page 11

... By utilizing 50% of the device, a midpoint is defined for From this midpoint, a designer may scale the I CC graphs up or down to estimate the I CC requirements for a particular design. 2-194 Frequency (MHz) I vs. Frequency CC PALCE20RA10 Family PALCE20RA10 Family 15434H-16 50 ...

Page 12

... ENDURANCE CHARACTERISTICS The PALCE20RA10 is manufactured using our ad- vanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Symbol Parameter t Min Pattern Data Retention Time DR N Min Reprogramming Cycles Robustness The PALCE20RA10 has been designed with some unique features that make it extremely robust, even when operating in high-speed design environments ...

Page 13

... POWER-UP RESET The PALCE20RA10 has been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This fea- ture provides extra flexibility to the designer and is espe- cially valuable in simplifying state machine initialization ...

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