adv202 Analog Devices, Inc., adv202 Datasheet - Page 30

• Manufacturer Part Number: adv202
• Description: Jpeg2000 Video Codec
• Manufacturer: Analog Devices, Inc.

ADV202
INDIRECT REGISTERS
In certain modes, such as custom-specific input format or HIPI
mode, indirect registers must be accessed by the user through
the use of the IADDR and IDATA registers. The indirect
register address space starts at Internal Address 0xFFFF0000.
Table 20. Indirect Registers
Address
0xFFFF0400
0xFFFF0404
0xFFFF0408
0xFFFF040C
0xFFFF0410
0xFFFF0414
0xFFFF0418
0xFFFF041C
0xFFFF0420
0xFFFF0424
0xFFFF0428
0xFFFF042C
0xFFFF0430
0xFFFF0440
0xFFFF0444
0xFFFF0448
0xFFFF044C
0xFFFF1408
0xFFFF140C
0xFFFF1410
0xFFFF1414
0xFFFF1418
0xFFFF141C
0xFFFF1420
0xFFFF1428 to 0xFFFF14FC
Name
PMODE1
COMP_CNT_STATUS
LINE_CNT_STATUS
XTOT
YTOT
F0_START
F1_START
V0_START
V1_START
V0_END
V1_END
PIXEL_START
PIXEL_END
MS_CNT_DEL
Reserved
PMODE2
VMODE
EDMOD0
EDMOD1
FFTHRP
Reserved
Reserved
FFTHRC
FFTHRA
Reserved
Rev. C | Page 30 of 40
Both 32-bit and 16-bit hosts can access the indirect registers.
32-bit hosts use the IADDR and IDATA registers, while the
16-bit hosts use IADDR, IDATA, and the stage register.
For additional information on accessing and configuring these
registers, see the
Description
Pixel/Video Format
Horizontal Count
Vertical Count
Total Samples per Line
Total Lines per Frame
Start Line of Field 0 [F0]
Start Line of Field 1 [F1]
Start of Active Video Field 0 [F0]
Start of Active Video Field 1 [F1]
End of Active Video Field 0 [F0]
End of Active Video Field 1 [F1]
Horizontal Start of Active Video
Horizontal End of Active Video
Master/Slave Delay
Reserved
Pixel Mode 2
Video Mode
External DMA Mode Register 0
External DMA Mode Register 1
FIFO Threshold for Pixel FIFO
Reserved
Reserved
FIFO Threshold for CODE FIFO
FIFO Threshold for ATTR FIFO
Reserved
ADV202 User’s
Guide.