isp1160 NXP Semiconductors, isp1160 Datasheet
isp1160
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isp1160 Summary of contents
Page 1
... The ISP1160 is well suited for embedded systems and portable devices that require a USB host. The ISP1160 brings high flexibility to the systems that have it built-in. For example, a system that has the ISP1160 built-in allows connected to a device that has a USB upstream port, such as a USB printer, USB camera, USB keyboard, USB mouse, among others ...
Page 2
... LQFP64 plastic low profile quad flat package; 64 leads; body 10 [1] LQFP64 plastic low profile quad flat package; 64 leads; body 7 [2] Improvement in performance as compared to ISP1160BD. Improvement in performance as compared to ISP1160BM. Rev. 05 — 24 December 2004 Embedded USB Host Controller 10 1 1.4 mm © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 3
... H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 16 63, 64 ISP1160 D0 to D15 22 RD_N 21 CS_N 23 MICROPROCESSOR WR_N 59 BUS INTERFACE A0 27 DACK_N 34 EOT 25 DREQ 29 INT 32 RESET_N POWER-ON RESET 56 VOLTAGE V CC REGULATOR 1, 8, 15, 18, 35, 45 DGND AGND Fig 1. Block diagram. ATL RAM ITL0 ITL1 ...
Page 4
... D9 10 D10 11 D11 12 D12 13 D13 14 15 D14 16 (1) ISP1160/01 is the marking on the IC for the ISP1160BD/01 and 1160/01 is the marking on the IC for the ISP1160BM/01. Pin description LQFP64 [1] Pin Type Description 1 - digital ground 2 I/O bit 2 of bidirectional data; slew-rate controlled; TTL input; three-state output ...
Page 5
... V, this pin can either be connected to 3 left unconnected. In all cases, decouple this pin to DGND DMA request output (programmable polarity); signals to the DMA controller that the ISP1160 wants to start a DMA transfer; see Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller pins. When V ...
Page 6
... NDP field in the HcRhDescriptorA register; both ports will always be enabled; see (internal pull-up resistor DMA master device to inform the ISP1160 of end of DMA transfer; active level is programmable; when not in use, this pin must be connected to V resistor; see 35 - ...
Page 7
... Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. Rev. 05 — 24 December 2004 Embedded USB Host Controller …continued REG(3V3) . When connected to 3 will bypass the internal © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 , V and HOLD1 is connected CC is connected to ...
Page 8
... FIFO buffer RAM. Therefore, the ISP1160 occupies only two I/O ports or two memory locations of a microprocessor. External microprocessors can read from or write to the ISP1160’s internal control registers and FIFO buffer RAM through the Programmed I/O (PIO) operating mode. Programmed I/O interface between a microprocessor and the ISP1160. ...
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... Fig 3. Programmed I/O interface between a microprocessor and the ISP1160. 8.2 DMA mode The ISP1160 also provides the DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by the DMA operation between a microprocessor’s system memory and the ISP1160’s internal FIFO buffer RAM. ...
Page 10
... The ISP1160’s register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1160 to the next register to be accessed. A command is 8 bits long microprocessor’s 16-bit data bus, a command occupies the lower byte, with the upper byte fi ...
Page 11
... Philips Semiconductors Fig 6. 16-bit register access cycle. Most of the ISP1160’s internal control registers are 16-bit wide. Some of the internal control registers, however, are 32-bit wide. internal control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor fi ...
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... FIFO buffer RAM access by DMA mode The DMA interface between a microprocessor and the ISP1160 is shown in When doing a DMA transfer, at the beginning of every burst the ISP1160 outputs a DMA request to the microprocessor via pin DREQ. After receiving this signal, the microprocessor will reply with a DMA acknowledge to the ISP1160 via pin DACK_N, and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1160’ ...
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... N 1/2 byte count of transfer data, K Fig 11. DMA transfer in burst mode. In Figure 10 HIGH and DACK_N is active LOW. 8.6 Interrupts The ISP1160 has an interrupt request pin INT. 8.6.1 Pin configuration The interrupt output signals have four configuration modes: Mode 0 Mode 1 Mode 2 Mode 3 9397 750 13963 ...
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... INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns Mode 3 edge triggered, active HIGH Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Section 10.4.1), which is also clear or disable INT clear or disable INT MGT944 Figure 13. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 15
... InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1160 Host Controller, the following procedure should be followed: 1. Make sure that the InterruptPinEnable bit in the HcHardwareConfiguration 2. Clear all bits in the Hc PInterrupt register. ...
Page 16
... Host Controller (HC) 9.1 HC’s four USB states The ISP1160’s USB HC has four USB states—USBOperational, USBReset, USBSuspend and USBResume—that define the HC’s USB signalling and bus states responsibilities. The signals are visible to the Host Controller Driver (HCD) via the ISP1160 USB HC’ ...
Page 17
... It is caused by the HostControllerReset field of the HcCommandStatus register (02H to read, 82H to write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1160 USB the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl register before generating USB traffi ...
Page 18
... HcSoftwareReset command (A9H). The reset function will clear all the HC’s internal control registers to their reset status. After reset, the HCD must initialize the ISP1160 USB HC by setting some registers. It includes: a. Setting the physical size for the HC’s internal FIFO buffer RAM by setting the HcITLBufferLength register (2AH to read, AAH to write) and the HcATLBufferLength register (2BH to read, ABH to write) ...
Page 19
... The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1160’s HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM ...
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... Format Byte 7 9397 750 13963 Product data ActualBytes[7:0] MaxPacketSize[7:0] TotalBytes[7:0] B5_5 reserved FunctionAddress[6:0] reserved Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Active Toggle ActualBytes[9:8] Last Speed MaxPacketSize[9:8] DirectionPID[1:0] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 0 ...
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... Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaximumPacketSize. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Description © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 22
... This bit is logic 0 at power-on reset. When this feature is not used, software used for the ISP1160 is the same for the ISP1161 and the ISP1161A. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only one PTD USB transaction will be sent out ...
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... ITL buffer ITL1 ISO_B control/bulk/interrupt ATL buffer ATL not used bottom 8 1280 1440 bytes. 8 150 1 1350 bytes. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller 200H. 0H. programmable sizes data 4 kbytes MGT950 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 24
... Remark: The PTD is defined for both the ATL and ITL type data transfer. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1160 takes care of the Ping-Pong action for the ITL buffer RAM access. Fig 18. Buffer RAM data organization. ...
Page 25
... Operation and C program example Figure 20 PIO mode. The ISP1160 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H to read, C0H to write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H to read, C1H to write) ...
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... Rev. 05 — 24 December 2004 Embedded USB Host Controller Commands Command register EOT internal EOT toggle SOF T BufferStatus Pointer 000H automatically 001H increments by 2 7FFH ATL buffer RAM MGT951 (8-bit width) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 ...
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... HcRegWrite(wHcTransferCounter,0x50); wCount (HcCmdPort,0x00c1); //Command for ATL buffer write 9397 750 13963 Product data 0x28; //Get word count outport Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller xH.\n",wData); Comments microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... ITL0BufferFull and ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the beginning of the fourth frame) the 9397 750 13963 Product data Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Table 5). © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... N 1) (frame N 2) (Figure 23), the ISO part is still being written while the Start of Frame 1 (depending on whether the exact timing data Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller (frame N 3) MGT954 1) is raised result, there will the AT N ...
Page 31
... Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built in the ISP1160 for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15Kresistorsel) of the HcHardwareConfi ...
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... ISP1160 bit 12 HcHardware Configuration internal 004aaa064 Using either internal or external 15 k resistors. shows the ISP1160 downstream port power management scheme. regulator 3 detect H_OCn_N H_PSWn_N ’n’ represents the downstream port numbers ( 2). Rev. 05 — 24 December 2004 ...
Page 33
... BUS ). For the internal overcurrent detection OC , H_PSWn_N will output a HIGH level, trip regulator HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE bit 12 HcHardware Configuration 15 k ISP1160 (2 ) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 to BUS of DSon 004aaa066 ...
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... Figure 14 for the HC’s flow of USB state changes. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE HcHardware Configuration ISP1160 004aaa067 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 35
... In the suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to power-down mode. The ISP1160 suspend and resume clock scheme is shown in Figure Pin H_SUSPEND is the sensing output pin for the HC’s suspended state. When the HC goes into the USBSuspend state, this pin will output a HIGH level (logic 1) ...
Page 36
... Philips Semiconductors Wake-up by pin CS_N (software wake-up): external microprocessor issues a chip select signal through pin CS_N to the ISP1160. This method of access to the ISP1160 internal registers is a software wake-up. Wake-up by USB devices: root hub port issues a resume signal to the HC through the USB bus, switching the HC from the USBSuspend state to the USBResume state ...
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... reserved reserved Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Functionality HC Root Hub registers HC DMA and interrupt control registers HC miscellaneous registers HC buffer RAM control registers ...
Page 38
... R/W R reserved R/W R reserved R/W R R/W R/W Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller R/W R/W R R/W R/W R RWE RWC ...
Page 39
... The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 40
... This bit, when set, does not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports. Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller ...
Page 41
... StartOfFrame: At the start of each frame, this bit is set by the HC and an SOF generated. - reserved SO SchedulingOverrun: This bit is set when USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller R/W R/W ...
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... FNO R/W R/W Rev. 05 — 24 December 2004 Embedded USB Host Controller reserved R/W R/W R R/W R/W R R/W R/W R reserved R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 ...
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... Scheduling Overrun R/W R reserved R/W R reserved R/W R/W Rev. 05 — 24 December 2004 Embedded USB Host Controller reserved R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 ...
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... Scheduling Overrun R/W R/W Rev. 05 — 24 December 2004 Embedded USB Host Controller reserved 0 0 R/W R/W R FSMPS[14: R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 R R ...
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... Rev. 05 — 24 December 2004 Embedded USB Host Controller R/W R/W R FI[13: R/W R/W R R/W R/W R reserved © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 ...
Page 46
... SOF reserved reserved FN[15: Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller FR[13: ...
Page 47
... The HC will set bit StartofFrame in the HcInterruptStatus register reserved R/W R reserved R/W R reserved R/W R LST[7: R/W R/W Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller R/W R/W R R/W R/W R LST[10: R/W R/W R/W ...
Page 48
... The transaction is started only if FrameRemaining value is calculated by the HCD, which considers transmission and set-up overhead. HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1:NDP] Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller this field. The © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Rev. 05 — 24 December 2004 Embedded USB Host Controller R/W R/W R R/W R/W R OCPM DT NPS IS 0 R ms. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 R R PSM NDP[1: ...
Page 50
... If the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower). - reserved NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by the ISP1160 reserved N/A N/A R ...
Page 51
... Rev. 05 — 24 December 2004 Embedded USB Host Controller DR[2:0] N R/W R/W 0), this field is not valid reserved OCIC R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 LPSC 0 R ...
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... Embedded USB Host Controller reserved OCI 0), this bit is written to logic 1 to turn on 0), this bit is written to logic 1 to turn off © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 LPS 0 R ...
Page 53
... This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 — no change in PortOverCurrentIndicator 1 — PortOverCurrentIndicator has changed Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller ...
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... On write—ClearPortPower: The HCD clears bit PortPowerStatus by writing a logic 1 to this bit. Writing a logic 0 has no effect. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 55
... ClearSuspendStatus: The HCD writes a logic 1 to initiate a resume. Writing a logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller …continued 0), only 1), if bit PortPowerControlMask[NDP] for © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 56
... PortEnableStatus. Writing a logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemoveable[NDP]). Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 57
... HIGH DACKInputPolarity 0 — active LOW 1 — reserved DREQOutputPolarity 0 — active LOW 1 — active HIGH DataBusWidth[1:0] These bits are fixed at logic 0 and logic 1 for the ISP1160. 01 — 16 bits Others — reserved Rev. 05 — 24 December 2004 Embedded USB Host Controller ...
Page 58
... This bit will be reset to logic 0 when DMA transfer is completed. - reserved Rev. 05 — 24 December 2004 Embedded USB Host Controller …continued R/W R/W R reserved DMA ITL_ATL_ Counter DataSelect Select R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 8 0 R/W 0 DMARead WriteSelect 0 R ...
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... R/W R Counter value R/W R/W HcTransferCounter register: bit description Symbol Description Counter The number of data bytes to be read to or written from RAM. value Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller …continued R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 60
... HcInterrupt registers to detect type of interrupt on the HC (if the HC requires the operational register to be updated). - reserved Rev. 05 — 24 December 2004 Embedded USB Host Controller R/W R/W R reserved AIIEOT ATLInt Interrupt R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 8 0 R/W 0 SOFITLInt 0 R ...
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... Interrupt Enable Enable R/W R/W Rev. 05 — 24 December 2004 Embedded USB Host Controller …continued Section 9. R/W R/W R reserved EOT ATL Interrupt Interrupt Enable Enable R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 8 0 R/W 0 SOF Interrupt Enable 0 R ...
Page 62
... HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1160 silicon chip. The higher byte stands for the product name. The lower byte indicates the revision number of the product including engineering samples. Code (Hex): 27 — read Table 46: ...
Page 63
... Bit 15 Symbol Reset 0 Access W Bit 7 Symbol Reset 0 Access W Table 51: Bit 9397 750 13963 Product data HcChipID register: bit description Symbol Description ChipID[15:0] ISP1160’s chip Scratch[15: R/W R Scratch[7: R/W R/W HcScratch register: bit description Symbol Description Scratch[15:0] ...
Page 64
... ITLBufferLength[7: R/W R/W HcITLBufferLength register: bit description Symbol Description ITLBufferLength[15:0] Assign ITL buffer length ITL1 (length ATLBufferLength[15: R/W R/W Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller 1000H (that is, 4 kbytes) ITL1 buffer length R/W R/W R R/W R/W R/W ATL (length) 1000H bytes ...
Page 65
... Rev. 05 — 24 December 2004 Embedded USB Host Controller R/W R/W R ITL0Buffer ATLBuffer ITL1Buffer Done Full Full © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 ITL0Buffer Full ...
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... R R Description The number of bytes for ITL0 data to be read back by the microprocessor Description the microprocessor. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 ...
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... Read/write ITL buffer RAM’s two data bytes DataWord[15: R/W R DataWord[7: R/W R/W HcATLBufferPort register: bit description Symbol Description DataWord[15:0] Read/write ATL buffer RAM’s two data bytes. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller R/W R/W R R/W R/W R ...
Page 68
... HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 data word). 9397 750 13963 Product data Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 69
... REG(3V3) V HOLD1 V HOLD2 Fig 29. Using supply. 12. Crystal oscillator The ISP1160 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See Figure ISP1160 XTAL2 XTAL1 Fig 31 ...
Page 70
... PORP (1) PORP = power-on reset pulse. POR EXTERNAL CLOCK Stable external clock is available at A. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller X, when V is 3.3 V. The time X depends on CC (2.03 V). The time X is decided by the trip Figure 33 shows a possible curve of drops below V ...
Page 71
... Rev. 05 — 24 December 2004 Embedded USB Host Controller Min Max 0.5 6.0 0.5 4.6 0.5 6.0 - 100 CC [1] 2000 2000 60 150 Min Typ 4.0 5.0 3.0 3.3 [ © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 Unit Max Unit 5.5 V 3.6 V 5 ...
Page 72
... suspend supply current CC(susp [1] In the suspend mode, the minimum voltage is 2.7 V. [2] For details on power consumption, refer to Philips Application Note AN10022 ISP1160x Low Power Consumption . Table 69: Static characteristics: digital pins Symbol Parameter Input levels ...
Page 73
... H_D and H_D . Rev. 05 — 24 December 2004 Embedded USB Host Controller Min Typ Max [1] 0 0 0.8 2 0.3 2 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 Unit ...
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... GND amb Conditions Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Min Typ Max 160 - - [ 100 - 500 pF; see Figure 42 for test circuit ...
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... WR_N data set-up time WDSU t WR_N data hold time WDH 9397 750 13963 Product data Conditions Min 5 8 300 110 143 110 136 Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Typ Max Unit - - ...
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... RLRH t RHRL t RLDV data data valid valid t WHWL WDH data data valid valid Conditions Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller t SLRL t SLWL t RHSH t WHSH RHDZ data data valid valid WDSU data data valid valid ...
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... Embedded USB Host Controller SHAH t AHRH t RHDZ data valid data valid t WSU t WHD Min Typ Max 102 - - [ 105 - - 150 - - 167 - - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 004aaa371 Unit ...
Page 78
... RHRL RLRH DREQ DACK_N RD_N or WR_N EOT t RLIS 0 ns DREQ DACK_N RD_N or WR_N EOT t RLIS 0 ns Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller SLRL t SHAH 004aaa372 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 004aaa373 004aaa374 ...
Page 79
... The address line A0 is needed for a complete addressing of the ISP1160 internal registers: • The CS_N line is used for chip selection of the ISP1160 in a certain address range of the RISC system. This signal is active LOW. • RD_N and WR_N are common read and write signals. These signals are active LOW ...
Page 80
... It is best to connect all four power supply pins (V V REG(3V3) Section ISP1160 the flexibility to be used in an embedded system under either a 3 power supply. A typical SH7709 interface circuit is shown in 18.3 Typical software model This section shows a typical software requirement for an embedded system that incorporates the ISP1160 ...
Page 81
... PRINTING CLASS DRIVER RISC ROM RAM LEN CONTROL Fig 41. The ISP1160 software model for DSC application. 19. Test information The dynamic characteristics of the analog I/O pins D and D as listed in were determined using the circuit shown in Fig 42. Load impedance. 9397 750 13963 Product data ...
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... MS-026 Rev. 05 — 24 December 2004 Embedded USB Host Controller detail 0.75 1.45 1 0.2 0.12 0.1 0.45 1.05 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 SOT314 ( 1.05 0 ISSUE DATE 00-01-19 03-02- ...
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... MS-026 Rev. 05 — 24 December 2004 Embedded USB Host Controller detail 0.75 0.64 1 0.2 0.08 0.08 0.45 0.36 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 SOT414 ( 0.36 0 ISSUE DATE 00-01-19 03-02- ...
Page 84
... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Rev. 05 — 24 December 2004 Embedded USB Host Controller 2.5 mm 350 called small/thin packages. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 3 so called ...
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... Rev. 05 — 24 December 2004 Embedded USB Host Controller Soldering method Wave not suitable [4] not suitable suitable [5][6] not recommended [7] not recommended [8] not suitable © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1160 [2] Reflow suitable suitable suitable suitable suitable not suitable ...
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... LQFP64”: in the description for pin 60, changed address A1 to A2. Section 9.8.1 “Using an internal OC detection sentence, changed source to drain and drain to source. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller 10 C measured in the atmosphere of the reflow circuit”: fourth paragraph, second © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 87
... SoftConnect — trademark of Koninklijke Philips Electronics N.V. StrongARM — registered trademark of ARM Ltd. SuperH — trademark of Hitachi Ltd. Rev. 05 — 24 December 2004 ISP1160 Embedded USB Host Controller Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 88
... Date of release: 24 December 2004 Document order number: 9397 750 13963 Embedded USB Host Controller 17.2 DMA timing Application information . . . . . . . . . . . . . . . . . 79 18.1 Typical interface circuit . . . . . . . . . . . . . . . . . . 79 18.2 Interfacing a ISP1160 to a SH7709 RISC processor 18.3 Typical software model . . . . . . . . . . . . . . . . . . 80 19 Test information Package outline . . . . . . . . . . . . . . . . . . . . . . . . 82 21 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 21.1 Introduction to soldering surface mount packages ...