isp1582 NXP Semiconductors, isp1582 Datasheet
isp1582
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isp1582 Summary of contents
Page 1
... The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1582 also incorporates features such as SoftConnect, a reduced frequency crystal oscillator, and integrated termination resistors. These features allow significant cost savings in system design and easy implementation of advanced USB functionality into PC peripherals ...
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... ISP1582BS HVQFN56 ISP1582_6 Product data sheet Description plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 8 0.85 mm Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Ref. 2 “On-The-Go ) BUS Version SOT684-1 © NXP B.V. 2007. All rights reserved ...
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... CC supply REGULATORS 3.3 V 13, 26, 29 28, 50 DGND AGND VCC1V8 SUSPEND WAKEUP Fig 1. Block diagram 12 MHz XTAL1 XTAL2 52 51 DMA ISP1582 HANDLER MEMORY NXP SIE/PIE DMA MANAGEMENT REGISTERS UNIT INTEGRATED MICRO- RAM CONTROLLER (8 kB) HANDLER SYSTEM OTG SRP CONTROLLER MODULE I/O pad supply ...
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... USB D+ line connection (analog USB D line connection (analog analog ground 6 A external bias resistor connection; connect to the external bias resistor; must be connected to ground through a 12.0 k resistor Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller 42 DATA10 41 DGND 40 DATA9 39 DATA8 38 DATA7 37 ...
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... Hi-Speed USB Peripheral Controller for power-on reset (internal POR circuit) CC through resistor CC(I/O) and Table 51 through resistor; see CC(I/O) and Table 51 through resistor; see CC(I/O) and Table 51 through resistor; see CC(I/O) and Table 51 ISP1582 © NXP B.V. 2007. All rights reserved ...
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... TTL tolerant 44 I/O bit 12 of bidirectional data bus bidirectional pad slew-rate control; TTL tolerant Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller 0.15 V); tapped out voltage © NXP B.V. 2007. All rights reserved ...
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... CMOS output drive exposed - ground supply; down bonded to the exposed die pad (heat die pad sink connected to DGND during PCB layout Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Section 7.14 0.15 V); tapped out voltage Section 7.16 Table 78 Table 78 0.3 V); this pin supplies the internal Section 7.16 0.3 V) ...
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... Optional double buffering increases the data throughput of these data endpoints. The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal 1.8 V regulator to power the digital logic. The ISP1582 operates MHz crystal oscillator. An integrated 40 multiplier generates the internal sampling clock of 480 MHz ...
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... RREF and ground to ensure an accurate current mirror that generates the Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the ISP1582 compliant to Hi-Speed USB and Original USB, supporting both the high-speed and full-speed physical layers. After automatic speed detection, the NXP Serial Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling ...
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... The ISP1582 handles more than one electrical state, Full-Speed (FS) or High-Speed (HS), under the USB specification. When the USB cable is connected from the peripheral to the Host Controller, the ISP1582 defaults to the FS state, until it sees a bus reset from the Host Controller. During the bus reset, the peripheral initiates an HS chirp to detect whether the Host Controller supports Hi-Speed USB or Original USB ...
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... The ISP1582 endpoints have a limitation when implementing a composite device with at least two functionalities that require the support of alternate settings, for example, the video class and audio class devices. The ISP1582 endpoints cannot be reconfigured on the fly because it is implemented as a FIFO base. The internal RAM partition will be corrupted if there is a need to reconfi ...
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... Plug-in: The USB cable is being plugged-in and V 7.13 Interrupt 7.13.1 Interrupt output pin The Interrupt Configuration register of the ISP1582 controls the behavior of the INT output pin. The polarity and signaling mode of pin INT can be programmed by setting bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT ...
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... INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of INT signals for the OUT pipe; see Table ISP1582_6 Product data sheet 22. Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved ...
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DMA Interrupt Reason register EXT_EOT INT_EOT DMA_XFER_OK DMA Interrupt Enable register IE_EXT_EOT OR IE_INT_EOT IE_DMA_XFER_OK Fig 3. Interrupt logic Interrupt Enable register IEBRESET IESOF IEDMA IEP7RX IEP7TX OR Interrupt register BRESET SOF DMA EP7RX EP7TX LE LATCH Interrupt Configuration register ...
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... SOF asserted) Pin INT: HIGH = de-assert; LOW = assert (individual interrupts are enabled). pin is one of the ways to wake up the clock when the ISP1582 is suspended Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller Section 8.2.2, Section 8.2.5 ...
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... NXP Semiconductors Fig 5. Resistor and electrolytic or tantalum capacitor needed for V Fig 6. Oscilloscope reading: no resistor and capacitor in the network Fig 7. Oscilloscope reading: with resistor and capacitor in the network 7.15 Power-on reset The ISP1582 requires a minimum pulse width of 500 s. ISP1582_6 Product data sheet 49 ISP1582 ...
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... The dip is too short (< and the internal POR pulse will not react and will remain LOW. t0 Fig 8. POR timing Figure 9 Fig 9. Clock with respect to the external POR 7.16 Power supply The ISP1582 can be powered by 3.3 V details, see If the ISP1582 is powered by V provides a 1.8 V supply voltage for the internal logic. ISP1582_6 Product data sheet curve (Figure 8) ...
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... F standard electrolytic or tantalum capacitors (tested ESR should the VCC1V8 output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 F LOW ESR capacitors (ESR from 0.2 high-speed signal quality at the USB side. shows power modes in which the ISP1582 can be operated. Power modes V CC(I/O) ...
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... NXP Semiconductors 7.16.1 Self-powered mode Fig 11. Self-powered mode In self-powered mode, V Table 6. ISP1582 operation Normal bus operation No pull- [1] When the USB cable is removed, SoftConnect is disabled. Table 7. ISP1582 operation Clock will wake up: After resume and After a bus reset Clock will wake up: After detecting the presence of V Table 8 ...
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... SRP is possible 7.16.2 Bus-powered mode 1. 3.3 V Fig 12. Bus-powered mode In bus-powered mode (see 5 V-to-3.3 V voltage regulator. The input to the regulator is from V USB cable, the ISP1582 goes through the power-on reset cycle. In this mode, OTG is disabled. Table 10. ISP1582 operation Normal bus operation Power loss Table 11 ...
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... NXP Semiconductors Table 12. ISP1582 operation Back voltage is not measured in this mode Power loss Table 13. ISP1582 operation SRP is not applicable Power loss ISP1582_6 Product data sheet Operation truth table for back voltage compliance Power supply Operation truth table for OTG ...
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... DREQ, DIOW, DIOR, EOT 50h shows reason (source) for DMA interrupt 2 54h enables DMA interrupt sources 58h selects endpoint FIFO, data flow direction 1 64h DMA burst counter Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Size Reference (bytes) 1 Section 8.2.1 on page 23 2 Section 8.2.2 ...
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... Test Mode PHY 8.1 Register access The ISP1582 uses a 16-bit bus access. For single-byte registers, the upper byte (MSByte) must be ignored. Endpoint specific registers are indexed using the Endpoint Index register. The target endpoint must be selected before accessing the following registers: • ...
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... Hi-Speed USB Peripheral Controller 3 2 DEVADDR[6: R/W R/W R/W Table 17 DMA CLKON - - - - GLINTENA WKUPCS PWRON 0 0 unchanged 0 R/W R/W R/W pin status. BUS ISP1582 R VBUSSTAT [ [ SOFTCT unchanged R/W © NXP B.V. 2007. All rights reserved ...
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... PWRON Power On: The SUSPEND pin output control. 0 — The SUSPEND pin is HIGH when the ISP1582 is in the suspend state. Otherwise, the SUSPEND pin is LOW. 1 — When the device is woken up from the suspend state, there will active HIGH pulse on the SUSPEND pin. The SUSPEND pin will remain LOW in all other states ...
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... DDBGMODOUT[1:0] — Interrupts for DATA OUT endpoints The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you to individually configure when the ISP1582 sends an interrupt to the external microprocessor. Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or falling edge ...
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... Once set, it remains at logic 1. To clear this bit, write logic 1. (The ISP1582 continuously updates this bit to logic 1 when the B-session is valid. If the B-session is valid after it is cleared set back to logic 1 by the ISP1582). 0 — It implies that SRP has failed. To proceed to a normal operation, the device can restart SRP, clear bit OTG or proceed to an error handling process. 1 — ...
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... NXP Semiconductors 8.2.4.1 Session Request Protocol (SRP) The ISP1582 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by V pulsing. The ISP1582 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to start SRP. 2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG register ...
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... Hi-Speed USB Peripheral Controller IEP7TX - - R IEP4TX IEP4RX IEP3TX R/W R/W R IEP0TX IEP0RX reserved R/W R/W R IESUSP IEPSOF IESOF R/W R/W R/W © NXP B.V. 2007. All rights reserved. ISP1582 24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W 0 IEBRST ...
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... Logic 1 enables interrupt on detection of a pseudo SOF. IESOF Logic 1 enables interrupt on detection of an SOF. IEBRST Logic 1 enables interrupt on detection of a bus reset EP0SETUP - R/W R/W Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller …continued sensing. BUS ENDPIDX[3: R/W R/W R/W © ...
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... R/W Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller ENDPIDX DIR 00h 0 00h 0 00h 1 0Xh 0 0Xh 1 Table 30. Register bits can stall, clear VENDP DSEN STATUS R/W W R/W © NXP B.V. 2007. All rights reserved. ISP1582 0 STALL ...
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... Remark: Use either bit VENDP or register Buffer Length to validate endpoint FIFO with FIFO bytes. DSEN Data Stage Enable: This bit controls the response of the ISP1582 to a control transfer. After the completion of the set-up stage, firmware must determine whether a data stage is required. For control OUT, firmware will set this bit and the ISP1582 goes into the data stage. Otherwise, the ISP1582 will NAK the data stage transfer. For control IN, fi ...
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... Description DATAPORT[7:0] data (lower byte) Table Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller R/W R/W R R/W R/W R/W 34. Table 38). A smaller value can be written when ISP1582 R R/W © NXP B.V. 2007. All rights reserved ...
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... R/W R DATACOUNT[7: R/W R/W Buffer Length register: bit description Symbol Description DATACOUNT[15:0] Data Count: Determines the current packet size of the indexed endpoint FIFO. Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller R/W R/W R ...
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... One of the buffers is filled. 10 — One of the buffers is filled. 11 — Both the buffers are filled NTRANS[1: R FFOSZ[7: R/W R/W Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller (AN10046)” BUF1 - - Table 38 FFOSZ[10: R/W ...
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... Table 39. Bit The ISP1582 supports all the transfers given in Rev. 2.0”. Each programmable FIFO can independently be configured using its Endpoint MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN plus OUT) including set-up token buffer, control IN and control OUT, must not exceed 8192 bytes ...
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... MSByte is written. Once the DMA transfer is started, the transfer counter starts decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated by the ISP1582. If the DMA master wishes to terminate the DMA transfer, it can issue an EOT signal to the ISP1582. This EOT signal overrides the transfer counter and can terminate the DMA transfer at any time ...
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... DMA_CMD[7: DMA Command register: bit description Symbol Description DMA_CMD[7:0] DMA command code; see Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Table Table 45. © NXP B.V. 2007. All rights reserved. ...
Page 39
... This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in For IN endpoint — Because there is a FIFO in the ISP1582 DMA controller, some data may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and the maximum delay time for data to be shifted to endpoint buffer is 60 ns. For OUT endpoint — ...
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... R/W R/W Description DMA transfer counter byte 4 (MSByte) DMA transfer counter byte 3 DMA transfer counter byte 2 DMA transfer counter byte 1 (LSByte) Table 48 MODE[1:0] reserved R/W R/W [1] ISP1582 R/W R R/W R WIDTH - R/W © NXP B.V. 2007. All rights reserved. ...
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... DACK strobes data from the DMA bus into the ISP1582; DIOR puts data from the ISP1582 on the DMA bus. 10 — DACK strobes data from the DMA bus into the ISP1582 and also puts data from the ISP1582 on the DMA bus. ...
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... GDMA Stop: When the GDMA_STOP command is issued to DMA Command registers, it means the DMA transfer has successfully terminated. Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller …continued EXT_EOT INT_EOT reserved R/W R/W R © NXP B.V. 2007. All rights reserved. ISP1582 8 DMA_ XFER_OK ...
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... Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller …continued Table 55. The bit description IE_EXT_ IE_INT_ reserved EOT EOT R/W R R/W R/W Table 56. ISP1582 9 8 IE_DMA_ XFER_OK R/W R R/W R/W © NXP B.V. 2007. All rights reserved ...
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... The value of the burst counter must be programmed so that the burst counter is a factor of the buffer size used to determine the assertion and de-assertion of DREQ. Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller EPIDX[2:0] ...
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... R/W R/W Interrupt register: bit description Symbol Description - reserved EP7TX logic 1 indicates the endpoint 7 TX buffer as interrupt source EP7RX logic 1 indicates the endpoint 7 RX buffer as interrupt source Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Table EP7TX - - R ...
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... Bus reset: Logic 1 indicates that a USB bus reset was detected. When bit OTG in the OTG register is set, BRESET will not be set, instead, this interrupt bit will report SE0 on DP and DM for 2 ms. Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller …continued Table 62. © ...
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... Chip ID: upper byte (82h) VERSION[7:0] Version: version number (30h MICROSOF[2: SOFR[7: Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller ...
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... Unlock Device register (address: 7Ch) To protect registers from getting corrupted when the ISP1582 goes into suspend, the write operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when the chip resumes, the Unlock Device command must first be issued to this register before attempting to write to the rest of the registers ...
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... RD_N, WR_N and CS_N signals maintain their states. When bit PWRON is logic 0, the RD_N, WR_N and CS_N signals are floating because the microprocessor is not powered. To protect the ISP1582 registers from being corrupted during suspend, register write is locked when the chip goes into suspend. Therefore, you need to issue the Unlock command to unlock the ISP1582 registers ...
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... A LI Conditions pins DP and +85 C; typical values at T amb Conditions high-speed full-speed CC(I/O) with voltage converter Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Min Max 0.5 +4.6 0.5 +4.6 [ 100 2000 +2000 40 +125 Min Typ Max 3 ...
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... DP is set in the OTG register = +85 C; unless otherwise specified. amb Conditions V V I(DP) I(DM) includes V range 1 3 GND < V < 3 Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Min Typ Max - - 0.3V CC(I/O) 0. CC(I/ 0.15V 0. CC(I/O) [1] 5 ...
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... test circuit of PU TERM Min Typ [ [1][2] 1.3 - 500 - 500 - © NXP B.V. 2007. All rights reserved. ISP1582 Unit pF M Unit s MHz Figure 22; Max Unit 111. ...
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... test circuit of PU TERM Min Typ [2] 160 - [ [2] 18 [2] Figure [ crossover point extended source EOP width: t receiver EOP width: t ISP1582 Figure 22; Max Unit 175 +18 EOPT EOPR mgr776 © NXP B.V. 2007. All rights reserved ...
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... JR consecutive transitions PERIOD JR1 paired transitions PERIOD JR2 3.3 V differential data lines +85 C. amb Conditions Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller t t JR1 JR2 t FST V IH(min) mgr872 Min Typ Max > RLDV ...
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... C to +85 C. amb Conditions T cy(RW) t SLWL t SLRL t RLDV t t AVRL RLRH t AVWL t DVWH t WLWH = +85 C. amb Conditions Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller …continued Min Typ Max WHSH t RHSH t WHAX t RHAX t RHDZ t WHDZ Min Typ ...
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... ISP1582_6 Product data sheet …continued = +85 C. amb Conditions cy1 t su3 su2 h3 Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Min Typ Max © NXP B.V. 2007. All rights reserved. Unit ns ...
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... ISP1582_6 Product data sheet su3 cy1 su2 cy1 su2 h3 Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller mgt502 mgt501 © NXP B.V. 2007. All rights reserved ...
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... In full-speed mode, an internal 1.5 k pull-up resistor is connected to pin DP. Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller 36 ns (min 004aaa928 ISP1582 address 8 A[7:0] data 16 DATA[15:0] RD_N WR_N CS_N 004aaa206 test point mgt495 ISP1582 © NXP B.V. 2007. All rights reserved ...
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... REFERENCES JEDEC JEITA MO-220 - - - Rev. 06 — 20 September 2007 Hi-Speed USB Peripheral Controller detail 2 scale 0.5 6.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION ISP1582 SOT684 ISSUE DATE 01-08-08 02-10-22 © NXP B.V. 2007. All rights reserved ...
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... Solder bath specifications, including temperature and impurities ISP1582_6 Product data sheet Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 24. Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Figure 24) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Memory Management Unit Non-Return-to-Zero Inverted On-The-Go Printed-Circuit Board Personal Digital Assistant Physical Packet IDentifier Parallel Interface Engine Parallel Input/Output Phase-Locked Loop Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved ...
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... USB 18. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB Specification Rev. 1.2 [3] ISP1581/2/3 Frequently Asked Questions (AN10046) [4] ISP1582/83 and ISP1761 clearing an IN buffer (AN10045) ISP1582_6 Product data sheet Abbreviations …continued Description Power-On Reset Single-Ended zero Serial Interface Engine ...
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... Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller Change notice Supersedes - ISP1582_5 2Ch)”: added two remarks. 28h)”: updated the DSEN bit. 20h)”: added two remarks. - ISP1582-04 200412038 ISP1582-03 - ISP1582-02 - ISP1582- © NXP B.V. 2007. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SoftConnect — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 22. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 3. ISP1582 pin status . . . . . . . . . . . . . . . . . . . . . .11 Table 4. ISP1582 output status . . . . . . . . . . . . . . . . . . .12 Table 5. Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 6. Operation truth table for SoftConnect . . . . . . .19 Table 7. Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 8. Operation truth table for back voltage compliance ...
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... Oscilloscope reading: with resistor and capacitor in the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Fig 8. POR timing .17 Fig 9. Clock with respect to the external POR . . . . . . . .17 Fig 10. ISP1582 with 3.3 V supply . . . . . . . . . . . . . . . . . .18 Fig 11. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .19 Fig 12. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .20 Fig 13. Source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Fig 14. Receiver differential data jitter . . . . . . . . . . . . . . .54 Fig 15 ...
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... Wave and reflow soldering . . . . . . . . . . . . . . . 60 16.3 Wave soldering 16.4 Reflow soldering Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 62 18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 64 20 Legal information . . . . . . . . . . . . . . . . . . . . . . 65 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 65 20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.3 Disclaimers 20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Rev. 06 — 20 September 2007 ISP1582 Hi-Speed USB Peripheral Controller continued >> © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1582 All rights reserved. Date of release: 20 September 2007 Document identifier: ISP1582_6 ...