isp1760 NXP Semiconductors, isp1760 Datasheet - Page 101

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
25. Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10: HCCPARAMS register: bit allocation . . . . . . . .29
Table 11: HCCPARAMS register: bit description . . . . . . .30
Table 12: USBCMD register: bit allocation . . . . . . . . . . .31
Table 13: USBCMD register: bit description . . . . . . . . . .31
Table 14: USBSTS register: bit allocation . . . . . . . . . . . .32
Table 15: USBSTS register: bit description . . . . . . . . . . .32
Table 16: USBINTR register: bit allocation . . . . . . . . . . .32
Table 17: USBINTR register: bit description . . . . . . . . . .33
Table 18: FRINDEX register: bit allocation . . . . . . . . . . .33
Table 19: FRINDEX register: bit description . . . . . . . . . .34
Table 20: CONFIGFLAG register: bit allocation . . . . . . .34
Table 21: CONFIGFLAG register: bit description . . . . . .35
Table 22: PORTSC1 register: bit allocation . . . . . . . . . . .35
Table 23: PORTSC1 register: bit description . . . . . . . . . .36
Table 24: ISO PTD Done Map register: bit description . .37
Table 25: ISO PTD Skip Map register: bit description . . .37
Table 26: ISO PTD Last PTD register: bit description . . .37
Table 27: INT PTD Done Map register: bit description . .37
Table 28: INT PTD Skip Map register: bit description . . .38
Table 29: INT PTD Last PTD register: bit description . . .38
Table 30: ATL PTD Done Map register: bit description . .38
Table 31: ATL PTD Skip Map register: bit description . . .39
Table 32: ATL PTD Last PTD register: bit description . . .39
Table 33: HW Mode Control register: bit allocation . . . . .39
Table 34: HW Mode Control register: bit description . . . .40
Table 35: Chip ID register: bit description . . . . . . . . . . . .41
Table 36: Scratch register: bit description . . . . . . . . . . . .41
Table 37: SW Reset register: bit allocation . . . . . . . . . . .41
Table 38: SW Reset register: bit description . . . . . . . . . .42
Table 39: DMA Configuration register: bit allocation . . . .42
Table 40: DMA Configuration register: bit description . . .43
Table 41: Buffer Status register: bit allocation . . . . . . . . .43
Table 42: Buffer Status register: bit description . . . . . . . .44
Table 43: ATL Done Timeout register: bit description . . .44
Table 44: Memory register: bit allocation . . . . . . . . . . . . .44
Table 45: Memory register: bit description . . . . . . . . . . .45
Table 46: Edge Interrupt Count register: bit allocation . .45
Table 47: Edge Interrupt Count register: bit description .46
9397 750 13257
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Memory address . . . . . . . . . . . . . . . . . . . . . . .15
Using the IRQ Mask AND or IRQ Mask OR
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Register overview . . . . . . . . . . . . . . . . . . . . . .27
CAPLENGTH register: bit description . . . . . . .28
HCIVERSION register: bit description . . . . . . .28
HCSPARAMS register: bit allocation . . . . . . . .28
HCSPARAMS register: bit description . . . . . . .29
Rev. 01 — 8 November 2004
Table 48: DMA Start Address register: bit allocation . . . 46
Table 49: DMA Start Address register: bit description . . 46
Table 50: Power Down Control register: bit allocation . . 47
Table 51: Power Down Control register: bit description . 47
Table 52: Port 1 Control register: bit allocation . . . . . . . . 49
Table 53: Port 1 Control register: bit description . . . . . . . 49
Table 54: Interrupt register: bit allocation . . . . . . . . . . . . 50
Table 55: Interrupt register: bit description . . . . . . . . . . . 50
Table 56: Interrupt Enable register: bit allocation . . . . . . 51
Table 57: Interrupt Enable register: bit description . . . . . 52
Table 58: ISO IRQ Mask OR register: bit description . . . 53
Table 59: INT IRQ Mask OR register: bit description . . . 53
Table 60: ATL IRQ Mask OR register: bit description . . . 54
Table 61: ISO IRQ Mask AND register: bit description . . 54
Table 62: INT IRQ Mask AND register: bit description . . 54
Table 63: ATL IRQ Mask AND register: bit description . . 55
Table 64: High-speed bulk IN and OUT, QHA: bit
Table 65: High-speed bulk IN and OUT, QHA: bit
Table 66: High-speed isochronous IN and OUT, iTD: bit
Table 67: High-speed isochronous IN and OUT, iTD: bit
Table 68: High-speed interrupt IN and OUT, QHP: bit
Table 69: High-speed interrupt IN and OUT, QHP: bit
Table 70: Start and complete split for bulk, QHASS/SC: bit
Table 71: Start and complete split for bulk, QHASS/SC: bit
Table 72: Start and complete split for isochronous, SiTD: bit
Table 73: Start and complete split for isochronous, SiTD: bit
Table 74: Start and complete split for interrupt: bit
Table 75: Start and complete split for interrupt: bit
Table 76: Power consumption . . . . . . . . . . . . . . . . . . . . . 82
Table 77: Absolute maximum ratings . . . . . . . . . . . . . . . 83
Table 78: Recommended operating conditions . . . . . . . . 83
Table 79: Static characteristics: digital pins . . . . . . . . . . 84
Table 80: Static characteristics: digital pins . . . . . . . . . . 84
Table 81: Static characteristics: PSW1_N, PSW2_N,
Table 82: Static characteristics: USB interface block (pins
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PSW3_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
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