isp1760 NXP Semiconductors, isp1760 Datasheet - Page 23

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isp1760

Manufacturer Part Number
isp1760
Description
Hi-speed Universal Serial Bus Host Controller For Embedded Applications
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
9397 750 13257
Product data sheet
7.7 Overcurrent detection
Additionally, the Power Down Control register allows the ISP1760 internal blocks to be
disabled for lower power consumption as defined in
The lowest suspend current that can be achieved is approximately 100 A at room
temperature. The suspend current will increase with the increase in temperature, with
approximately 300 A at 40 C and up to a typical 1 mA at 85 C. The system is not in
suspend mode when its temperature increases above 40 C. Therefore, even a 1 mA
current consumption by the ISP1760 (in suspend mode) can be considered negligible. In
normal environmental conditions, when the system is in suspend mode, the maximum
ISP1760 temperature will be approximately 40 C (determined by the ambient
temperature) so the ISP1760 maximum suspend current will be below 300 A. An
alternative solution to achieve a very low suspend current is to completely switch off the
V
pins of the processor. This is possible because the ISP1760 can be used in the hybrid
mode, which allows only the V
The time from wake-up to suspend will be approximately 100 ms when the ISP1760
power is always on.
It is necessary to wait for the CLK_RDY interrupt assertion before programming the
ISP1760 because internal clocks are stopped during deep-sleep suspend and restarted
after the first wake-up event. The occurrence of the CLK_RDY interrupt means that the
internal clocks are running and the normal functionality is achieved.
It is estimated that the CLK_RDY interrupt will be generated less than 100 s after the
wake-up event, if the power to the ISP1760 was on during suspend.
If the ISP1760 is used in the hybrid mode and V
pulse is required when the power is switched back to on, before starting to program the
resume state. This will ensure that the internal clocks are running and all logics reach a
stable initial state.
The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of
the HW Mode Control register can be programmed to select the analog or digital
overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The
main features of this circuit are self reporting, automatic resetting, low-trip time and low
cost. This circuit offers an easy solution at no extra hardware cost on the board. The port
power will be automatically disabled by the ISP1760 on an overcurrent event occurrence,
by deasserting the PSWn_N signal without any software intervention.
When using the integrated analog overcurrent detection, the range of the overcurrent
detection voltage for the ISP1760 is 45 mV to 100 mV. Calculation of the external
components should be based on the 45 mV value, with the actual overcurrent detection
threshold usually positioned in the middle of the interval.
For an overcurrent limit of 500 mA per port, a PMOS with R
is required. If a PMOS with a lower R
adjusted using a series resistor; see
V
CC(5V0)
PMOS
V
PMOS
= V
power input by using an external PMOS transistor, controlled by one of the GPIO
= voltage drop on PMOS
TRIP
= V
Rev. 01 — 8 November 2004
TRIP(intrinsic)
CC(I/O)
(I
powered on to avoid loading of the system bus.
Figure
DSON
OC(nom)
is used, analog overcurrent detection can be
5.
Embedded Hi-Speed USB host controller
R
CC(5V0)
td
), where:
Table
is off during suspend, a 2 ms reset
5.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
DSON
of approximately 100 m
ISP1760
23 of 105

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