isp1760 NXP Semiconductors, isp1760 Datasheet - Page 56

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13257
Product data sheet
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by the EHCI data structure, until it reaches the terminate bit
in a microframe. If a schedule is enabled, the Host Controller starts executing from the
ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule.
The EHCI periodic and asynchronous lists are traversed by the software according to the
EHCI traversal rule, and executed only from the asynchronous schedule after it
encounters the end of the periodic schedule. The Host Controller traverses the ISO, INTL
and ATL schedules. It fetches the element and begins traversing the graph of linked
schedule data structures.
The last bit identifies the end of the schedule for each type of transfer, indicating the rest
of the channels are empty. Once a transition is completed, the Host Controller executes
from the next transfer descriptor in the schedule until the end of the microframe.
The completion of a transfer is indicated to the software by the interrupt that can be
grouped over the various PTDs by using the AND or OR registers that are available for
each schedule type (ISO, INTL and ATL). These registers are simple logic registers to
decide the group and individual PTDs that can interrupt the CPU for a schedule, when the
logical conditions of the done bit is true in the shared memory that completes the interrupt.
Interrupts are of four types and the latency can be programmed in multiples of SOF
(125 s).
A static PTD that schedules inside the ISP1760 shared memory allows using the
NextPTD mechanism that will enable the Host Controller driver to schedule the multiple
PTDs that are of single endpoint and reduce the interrupt to the CPU.
The NextPTD traversal rules defined by the ISP1760 hardware are:
1. Start the ATL header traversal.
2. If the current PTD is active and not done, perform the transaction.
3. Follow the next link pointer.
4. If PTD is not active and done, jump to the next PTD.
5. If the next link pointer is NULL, it means the end of the traversal.
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ISO interrupt
INTL interrupt
ATL Interrupt
SOF—start of frame interrupt for the data transfer.
Rev. 01 — 8 November 2004
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
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