lan91c100 Standard Microsystems Corp., lan91c100 Datasheet
lan91c100
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lan91c100 Summary of contents
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... Support for 32, 16 and 8 Bit CPU Accesses Synchronous, Asynchronous and Burst DMA Interface Mode Options 128 Kbyte External Memory The LAN91C100 FEAST is a high-speed network controller designed to facilitate the implementation of Fast Ethernet adapters and connectivity products. It contains a dual speed CSMA/CD engine that implements the MAC ...
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FEATURES ........................................................................................................................................ 1 GENERAL DESCRIPTION .................................................................................................................. 1 PIN CONFIGURATION ....................................................................................................................... 3 DESCRIPTION OF PIN FUNCTIONS ................................................................................................. 4 FUNCTIONAL DESCRIPTION .......................................................................................................... 14 DATA STRUCTURES AND REGISTERS .......................................................................................... 17 BOARD SETUP INFORMATION ....................................................................................................... 59 APPLICATION CONSIDERATIONS .................................................................................................. 62 OPERATIONAL DESCRIPTION ........................................................................................................ 69 ...
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... The first is a conventional seven nLNK 1 TXEN 2 XTAL1 3 XTAL2 4 VDD 5 MIISEL 6 nCSOUT TX25 9 VDD 10 RX_ER 11 RX_DV 12 IOS0 13 GND 14 IOS1 15 IOS2 16 RX25 17 LAN91C100 COL100 18 CRS100 19 RXD0 20 RXD1 21 RXD2 22 VDD 23 RXD3 24 208 Pin PQFP TXD0 25 TXD1 26 VDD 27 TXD2 28 TXD3 29 TXEN100 30 nRWE0 31 GND 32 and TQFP RD7 33 ...
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... BUFFER TYPE DESCRIPTION I Input. Decoded by the LAN91C100 to determine accesses to its registers. I Input. Used by the LAN91C100 for internal register selection. I Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. I Input. Used during LAN91C100 register accesses to determine the width of the access and the register(s) being accessed ...
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... Write cycles when high, read cycles when low. IP Input. When low synchronous bus interface is configured for VL Bus accesses. LAN91C100 is configured for EISA DMA burst accesses. Does asynchronous bus interface. I Input. Used to interface synchronous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode. OD16 Open drain output ...
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... When nDATACS is low, the Data Path can be accessed regardless of the values of AEN, A1-A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C100 32 bits at a time. O4 Output. 4 sec clock used to shift data in and out of the serial EEPROM. O4 Output ...
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... RAM. O4 Outputs. Used to write any byte, word or dword in RAM. O4 Output. This pin LAN91C100 write memory cycles of receive packets external 25 MHz crystal is connected CLK across these pins TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open. ...
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DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS PQFP/TQFP PIN NO. NAME SYMBOL 14,32, Ground GND 46,50, 66,75, 82,94, 111,116, 120,122, 128,134, 138,169, 174,180, 185,200 203 Analog AGND Ground 2 Transmit TXEN Enable 201 Transmit TXD Data 208 Carrier CRS Sense ...
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DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS PQFP/TQFP PIN NO. NAME SYMBOL 1 nLink Status nLNK 195 nFullstep nFSTEP 6 MII Select MIISEL 194 AUI Select AUISEL 30 Transmit TXEN100 Enable 100 Mbps 19 Carrier 100 CRS100 Mbps 12 Receive ...
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... MII management data output. O4 MII management clock. ID Input. Indicates a code error detected by PHY. Used by the LAN91C100 to discard the packet being received. indication reported for this event is the same as a bad CRC (Receive Status Word bit 13). This pin is ignored when MIISEL is low. ...
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... Table 1 - LAN91C100 Pin Requirements FUNCTION System Address Bus A1-A15, AEN, nBE0-nBE3 System Data Bus D0-D31 System Control Bus RESET, nADS, LCLK, ARDY, nRDYRTN, nSRDY, INT0-INT3, nLDEV, nRD, nWR, nDATACS, nCYCLE, W/nR, nVLBUS Serial EEPROM EEDI, EEDO, EECS, EESK, ENEEP, IOS0-IOS2 RAM Data Bus ...
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12 ...
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... SERIAL EEPROM Address ARBITER Data BUS INTERFACE UNIT Control MEMORY MANAGEMENT UNIT RD WR FIFO FIFO RAM FIGURE 1 - LAN91C100 FEAST BLOCK DIAGRAM DIRECT MEMORY ACCESS MEDIA ACCESS CONTROL 25 MHz Interface 100 Mb Media Independent Interface ...
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... SERIAL EEPROM SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL LAN91C100 DATA DATA FEAST RA OE,WE RD0-31 SRAM 32kx8 2 1 FIGURE 2 - LAN91C100 FEAST SYSTEM DIAGRAM LAN83C694 1O Mbps 10BASE-T INTERFACE 100BASE-T4 INTERFACE MII OR 100BASE-TX INTERFACE 10BASE-T CHIP 100BASE-T4 100BASE-TX LOGIC ...
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... FUNCTIONAL DESCRIPTION DESCRIPTION OF BLOCKS Clock Generator Block The LAN91C100's clock generator uses a 25 MHz crystal connected to pins XTAL1 XTAL2 and generates two free running clocks MHz free running clock - Supplied to the DMA and the ARBITER blocks MHz free running clock - Used to run the EPH during reset or when no TX25 is present ...
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... MII Management Interface Block PHY management through the MII management interface is supported by the LAN91C100 by providing the means to drive a tri-statable data output, a clock, and reading an input. Timing and framing for each management command is be generated by the CPU ...
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... READ DATA DATA REG REG FIGURE 3 - LAN91C100 INTERNAL BLOCK DIAGRAM WITH DATA PATH by this block which, under CPU command, will program specific locations in the EEPROM. This block is an autonomous state machine, and it controls the LAN91C100's internal Data Bus during active operation. ...
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DATA STRUCTURES AND REGISTERS PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the Transmit and Receive areas. The first word is bit 15 RAM OFFSET (Decimal 2046 Max FIGURE 4 – DATA ...
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... The LAN91C100 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C100 treated transparently as data both for transmit and receive operations. CONTROL BYTE - For transmit packets the ...
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RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory not available as a register. HIGH ALGN BROD BYTE ERR CAST LOW BYTE 5 ALGNERR Frame had alignment error. When MII ...
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I/O SPACE The base I/O space is determined by the IOS0-2 inputs and the EEPROM contents. To limit the I/O space requirements to 16 locations, the registers are assigned to different banks. The OFFSET HIGH bit 15 bit14 BYTE X ...
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... BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. cycles where (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers. Note: BANK7 does not exist in LAN91C9x devices. For backward BANK7 accesses should be done if the Revision Control register LAN91C100. 22 SYMBOL BSR BS1 BS0 0 0 ...
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... NOCRC Does not append CRC to transmitted blocked: frames when set; allows software to insert the desired CRC. Defaults to 0 (CRC inserted). PAD_EN When set, the LAN91C100 will pad transmit frames shorter than 64 bytes with 00. Does not pad frames when reset. FORCOL When set, the transmitter will force a collision by not deferring deliberately ...
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I/O SPACE - BANK 0 OFFSET 2 EPH STATUS REGISTER This register stores the status of the last frame transmitted. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to ...
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Set if frame was broadcast. Cleared at the start of every transmit frame. SQET Signal Quality Error Test. For 10 Mbps systems, the transmitter opens a 1.6 s window 0.8 s after transmission is completed and the receiver returns inactive. ...
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... BYTE 0 0 SOFT_RST Software-activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. LAN91C100's configuration is not preserved except for Configuration, Base, and IA0-5 Registers. EEPROM is not reloaded after software reset. FILT_CAR Filter Carrier. When set, filters leading edge of carrier sense for 12 bit times (3 nibble times) ...
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I/O SPACE - BANK 0 OFFSET 6 COUNTER REGISTER Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register, and do not wrap around beyond 15. HIGH ...
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I/O SPACE - BANK 0 OFFSET 8 MEMORY INFORMATION REGISTER HIGH FREE MEMORY AVAILABLE (IN BYTES * 256 * M) BYTE 1 1 LOW BYTE 1 1 FREE MEMORY AVAILABLE This register can be read at any time to determine ...
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... This register defaults to zero upon reset not affected by the RESET MMU command. DEVICE bit 11 LAN91C100 0 LAN91C90 0 FUTURE 0 FUTURE 1 ...
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... MII SELECT Used to select the network interface port. When set, the LAN91C100 will use its MII port and interface a PHY device at the nibble rate. When clear, the LAN91C100 will use its 10 Mbps ENDEC interface. This bit drives the MII SEL pin. Switching between ports ...
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... I/O SPACE - BANK1 OFFSET 2 BASE ADDRESS REGISTER This register holds the I/O address decode option chosen for the LAN91C100. EEPROM saved setup, and is not usually modified during run-time. HIGH A15 A14 BYTE 0 0 LOW BYTE 0 0 A15-A13 and A9-A5 These bits are compared against the I/O address on the bus to determine the IOBASE for the LAN91C100's registers ...
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I/O SPACE - BANK1 OFFSET 4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a ...
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... EEPROM, that is normally protected from accidental Store operations. This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. EEPROM read and write routines that do not affect the basic setup of the LAN91C100. 33 SYMBOL GPR 0 0 ...
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I/O SPACE - BANK1 OFFSET C CONTROL REGISTER HIGH 0 RCV_BAD BYTE 0 0 LOW LE CR BYTE ENABLE ENABLE 0 0 RCV_BAD When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and ...
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... EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C100 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 sec. ...
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... N2,N1,N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2,N1,N0 are ignored by the LAN91C100 but should be implemented in the LAN91C100's software drivers for LAN9000 compatibility. 010 2) RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet FIFO pointers ...
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... Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory. Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C100 but should be used for Command 0) to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands ...
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I/O SPACE - BANK2 OFFSET 2 PACKET NUMBER REGISTER PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number ...
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I/O SPACE - BANK2 OFFSET 4 FIFO PORTS REGISTER This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from ...
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I/O SPACE - BANK2 OFFSET 6 POINTER REGISTER HIGH RCV AUTO BYTE INCR LOW BYTE 0 0 POINTER REGISTER The value of this register determines the address to be accessed within the transmit or receive areas. increment on ...
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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C100 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. ...
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I/O SPACE - BANK2 OFFSET C INTERRUPT STATUS REGISTER ERCV INT EPH INT OFFSET C INTERRUPT ACKNOWLEDGE ERCV INT OFFSET D INTERRUPT MASK REGISTER ERCV INT EPH INT This register can be read and ...
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The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these sources can be done via the Control Register. 43 ...
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The possible sources are: LINK - Link Test transition CTR_ROL - Statistics counter roll over TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by ...
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45 ...
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46 ...
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FIGURE 5 – INTERRUPT STRUCTURE 47 ...
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OFFSET 0 THROUGH 7 MULTICAST TABLE LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 I/O SPACE ...
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The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of the CRC of the destination addresses. The determine the register to be used (MT0-7), while the other ...
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I/O SPACE - BANK3 OFFSET 8 MANAGEMENT INTERFACE HIGH BYTE 0 0 LOW BYTE 0 0 MDOE MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated. MCLK MII Management clock. The value of ...
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... NAME TYPE READ ONLY REV Revision revision of a given device. DEVICE LAN91C90/LAN91C92 LAN91C100 NAME TYPE READ/WRITE ERCV THRESHOLD Whenever the number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT bit of the INTERRUPT STATUS REGISTER is set ...
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... I/O SPACE - BANK 7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C100 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE CYCLE AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 Otherwise NAME TYPE EXTERNAL R/W REGISTER EXTERNAL R/W REGISTER nCSOUT LAN91C100 DATA BUS Driven low ...
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TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit ...
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TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 ENABLE RECEPTION - By setting the RXEN bit SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet ...
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ISR Save Bank Select & Address Ptr Registers Mask SMC91C100 Interrupts Read Interrupt Register Yes Call TX INTR or TXEMPTY INTR Get Next TX Packet No Available for Transmission? Yes No Call ALLOCATE EPH INTR? Yes Call EPH INTR No ...
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FIGURE 6 – INTERRUPT SERVICE ROUTINE 56 ...
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RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes Destination No Multicast? Read Words from RAM for Address Filtering No Yes Address Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get ...
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TX INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes No TX Status OK? Update Statistics Re-Enable TXENA Immediately Issue "Release" ...
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FIGURE 8 – TX INTR 59 ...
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TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 0 TXEMPTY = X & & TXINT = 0 TXINT = 1 (Waiting for Completion) (Transmission Failed) Read Pkt. # Register & Save Write ...
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FIGURE 9 – TXEMPTY INTR (Assumes Auto Release Selected) 61 ...
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DRIVER SEND Choose Bank Select Issue "Allocate Memory" Register 2 Call ALLOCATE Read Interrupt Status Register Exit Driver Send Yes Read Allocation Result Register Write Allocated Packet into Packet # Register Write Address Pointer Register Copy Part of TX Data ...
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FIGURE 10 – DRIVER SEND AND ALLOCATE ROUTINES 63 ...
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... Note that with the memory management built into the LAN91C100, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...
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... TX DONE PACKET NUMBER at the FIFO PORTS register. eliminates the need for the driver to keep a list of packet numbers being transmitted. numbers are queued by the LAN91C100 and provided back to the CPU as their transmission completes. 2) One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1 ...
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INTERRUPT STATUS REGISTER RCV INT TX EMPTY TWO INT OPTIONS TX INT ALLOC INT 'EMPTY' 'NOT EMPTY' TX DONE PACKET NUMBER CPU ADDRESS M.S. BIT ONLY 'NOT EMPTY' PACKET NUMBER REGISTER CSMA ADDRESS PACK # OUT 66 RX FIFO PACKET ...
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FIGURE 11 – INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU 67 ...
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... In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C100. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, INTERRUPT) that can always be used regardless of the EEPROM based value being programmed ...
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On EEPROM write operations (after setting the STORE bit) the values of the CONFIGURATION REGISTER and BASE REGISTER are written in the EEPROM locations defined by the IOS2-0 pins. The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, ...
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IOS2-0 WORD ADDRESS 000 0h 1h 001 4h 5h 010 8h 9h 011 Ch Dh 100 10h 11h 101 14h 15h 110 18h 19h XXX 20h 21h 22h 70 16 BITS CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION ...
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FIGURE 12 – SERIAL EEPROM MAP 71 ...
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... Qualifies valid I/O decoding - enabled access when low. This signal is latched by nADS rising edge and transparent on nADS low time Direction of access. Sampled by the LAN91C100 on first rising clock that has nCYCLE active. High on writes, low on reads. Ready return. Direct connection to VL bus. ...
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... NOTES Local Bus Clock. Rising edges used for synchronous bus interface transactions. Connected via inverter to the LAN91C100. Byte enables. Latched transparently by nADS rising edge. Address Strobe is connected directly to the VL bus. nCYCLE is created typically by using nADS delayed by one LCLK. Typically uses the interrupt lines on the ISA edge connector of VL bus ...
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... HIGH-END ISA MACHINES On ISA machines, the LAN91C100 is accessed bit peripheral. No support for XT (8 bit Table 4 - High-End ISA Machines Signal Connections ISA BUS LAN91C100 SIGNAL SIGNAL A1-A15 A1-A15 AEN AEN nIORD nRD nIOWR nWR IOCHRDY ARDY RESET RESET A0 nBE0 nSBHE nBE1 ...
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... Table 4 - High-End ISA Machines Signal Connections ISA BUS LAN91C100 SIGNAL SIGNAL VCC nBE2, nBE3, nCYCLE, W/nR nRDYRTN GND LCLK, nADS OPEN D16-D31, nDATACS, nVLBUS NOTES UNUSED PINS No upper word access. 75 ...
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... EISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVEEISA 32 BIT SLAVE On EISA, the LAN91C100 is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C100 uses asynchronous accesses. In ...
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... Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application. Other combinations of nBE are not supported by the LAN91C100. S/W drivers are not anticipated to generate them. nLDEV is a totem pole output. nLDEV is active on valid decodes of the LAN91C100's pins A15-A4 and AEN=0 ...
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DMA mode to bring in EXRDY. 78 ...
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... Table 5 - EISA 32 Bit Slave Signal Connections EISA BUS SIGNAL LAN91C100 SIGNAL VCC nVLBUS GND A1 OPEN NOTES UNUSED PINS 79 ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ........................................................................................ 0ºC to +70ºC Storage Temperature Range ...................................................................................... -55ºC to +150ºC Lead Temperature Range (soldering, 10 seconds) ................................................................... +325ºC Positive Voltage on any pin, with respect to Ground ............................................................ V Negative Voltage ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage IP Type Buffers Input Current ID Type Buffers Input Current O4 Type Buffer Low Output Level High Output Level V Output ...
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PARAMETER SYMBOL OD16 Type Buffer Low Output Level Output Leakage O24 Type Buffer Low Output Level High Output Level Output Leakage I/O24 Type Buffer Low Output Level High Output Level Output Leakage Supply Current Active Supply Current Standby CAPACITANCE T ...
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ADDRESS nADS READ DATA nRD,nWR WRITE DATA FIGURE 13 - ASYNCHRONOUS CYCLE - nADS = 0 PARAMETER t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to nRD, nWR Active t2 A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive (Assuming ...
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FIGURE 14 - ASYNCHRONOUS CYCLE - USING nADS ADDRESS A1-A15, AEN,nBE0-nBE3 valid nADS READ DATA nRD, nWR WRITE DATA PARAMETER t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to nRD, nWR Active t3 nRD Low to Valid Data t4 ...
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FIGURE 15 - ASYNCHRONOUS CYCLE - nADS = 0 (nDATACS Used to Select Data Register; Must Be 32 Bit Access) nDATACS nADS READ DATA t1 nRD, nWR WRITE DATA PARAMETER t1 A1-A15, AEN, nBE0-nBE3 Valid and nADS Low Setup to ...
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FIGURE 16 - BURST WRITE CYCLES - nVLBUS = 1 LCLK nDATACS W/nR nCYCLE WRITE DATA nRDYRTN PARAMETER t12 nDATACS Setup to Either nCYCLE or W/nR Falling t13 nDATACS Hold after Either nCYCLE or W/nR Rising t14 nRDYRTN Setup to ...
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FIGURE 17 - BURST READ CYCLES - nVLBUS = 1 LCLK nDATACS W/nR READ DATA nRDYRTN nCYCLE PARAMETER t12 nDATACS Setup to Either nCYCLE or W/nR Falling t13 nDATACS Hold after Either nCYCLE or W/nR Rising t14 nRDYRTN Setup to ...
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FIGURE 18 - ADDRESS LATCHING FOR ALL MODES nADS ADDRESS nLDEV PARAMETER t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay t8 t9 A1-15,AEN,nBE0-nBE3 t25 MIN TYP ...
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FIGURE 19 - SYNCHRONOUS WRITE CYCLE - nVLBUS = 0 LCLK W/nR ADDRESS nADS nCYCLE WRITE DATA nSRDY nDATACS PARAMETER t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising t10 nCYCLE Setup to ...
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Hold after LCLK Rising (Non-Burst Mode) t16 W/nR Setup to nCYCLE Active t17A W/nR Hold after LCLK Rising with nLRDY Active t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t21 nLRDY Delay ...
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FIGURE 20 - SYNCHRONOUS READ CYCLE - nVLBUS = 0 LCLK W/nR ADDRESS A1-15,AEN,nBE0-nBE3 t8 nADS nCYCLE READ DATA nSRDY RDYRTN nDATACS t9 t10 t16 t11 D0-D31 valid t21 80 t20 t23 t24 t21 ...
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PARAMETER t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold After nADS Rising t10 nCYCLE Setup to LCLK Rising t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) t16 W/nR Setup to nCYCLE Active t20 Data Hold ...
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FIGURE 21 - SRAM INTERFACE t34 RA2-RA16 RnWE0-nRWE3 nROE RD0-RD31 WRITE CYCLE PARAMETER t34 RA2-RA16nn Setup to nRWE-0-nRWE3 Falling t35 RA2-RA16nn Hold After nRWE-0-nRWE3, nROE Rising t36 Write - RD0-RD31 Setup to nRWE0-nRWE3 Rising t37 Write - RD0-RD31 Hold after ...
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FIGURE 22 - ENDEC INTERFACE - 10 MBPS TXC t30 TXEN t30 TXD RXD RXC CRS PARAMETER t30 TXD, TXEN Delay from TXC Rising t31 nRXD Setup to RXC Rising t32 RXD Hold After RXC Rising Notes: 1. CRS input ...
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FIGURE 23 - MII INTERFACE TX25 TXD0-3 t27 TXEN100 RXD0-3 RX25 RX_DV RX_ER PARAMETER t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising t27 t28 t28 ...
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DETAIL ' 157 208 0. DIM Notes: 1 Coplanarity is ...
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FIGURE 24 - 208 PIN PQFP PACKAGE OUTLINES 86 ...
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DIM MIN NOM MAX A 1.60 A1 0.05 0.15 A2 1.35 1.45 D 29.80 30.00 30.20 D/2 14.90 15.00 15.10 D1 27.90 28.00 28.10 E 29.80 30.00 30.20 E/2 14.90 15.00 15.10 E1 27.90 28.00 28.10 H 0.09 0.23 L ...
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FIGURE 25 – 208 PIN TQFP PACKAGE OUTLINES 88 ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. LAN91C100 Rev. 9/24/97 ...