lan9420 Standard Microsystems Corp., lan9420 Datasheet - Page 73

• Manufacturer Part Number: lan9420
• Description: Lan9420/lan9420i Single-chip Ethernet Controller With Hp Auto-mdix Support And Pci Interface
• Manufacturer: Standard Microsystems Corp.

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.6.8.1
3.6.8.2
3.6.9
3.6.9.1
3.6.9.2
3.6.10
3.6.11
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the PHY, except the management
interface, is powered-down and stays in that condition as long as PHY register bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to
Control Register," on page 137
Note: For maximum power savings, auto-negotiation should be disabled before enabling the General
Energy Detect Power-Down
This power-down mode is activated by setting the PHY register bit 17.13 to 1. Please refer to
4.5.8, "Mode Control/Status," on page 144
no energy is present on the line, the PHY is powered down, with the exception of the management
interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON logic is used to detect
the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the internal ENERGYON signal is
asserted, and the PHY powers-up. It automatically resets itself into the state it had prior to power-down,
and asserts the
enabled, this event will cause a PHY interrupt to the Interrupt Controller and the power management
event detection logic.
The first and possibly the second packet to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
PHY Resets
In addition to a chip-level reset, the PHY supports two software-initiated resets. These are discussed
in the following sections.
PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This
self-clearing bit will return to ‘0’ after approximately 100μs, at which time the PHY reset is complete.
PHY Soft Reset via PHY Basic Control Register bit 15 (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register.
This self-clearing bit will return to ‘0’ after approximately 256μs, at which time the PHY reset is
complete. The BCR reset initializes the logic within the PHY, with the exception of register bits marked
as NASR (Not Affected by Software Reset).
Required Ethernet Magnetics
The magnetics selected for use with LAN9420/LAN9420i should be an Auto-MDIX style magnetic
available from several vendors. The user is urged to review SMSC Application Note 8.13 "Suggested
Magnetics" for the latest qualified and suggested magnetics. Vendors and part numbers are provided
in this application note.
PHY Registers
Please refer to
registers.
Power-Down mode.
Section 4.5, "PHY Registers," on page 136
INT7
bit of the PHY
for additional information on this register.
DATASHEET
Interrupt Source Flag
for additional information on this register. In this mode when
73
register. If the ENERGYON interrupt is
for a complete description of the PHY
Section 4.5.1, "Basic
Revision 1.1 (03-31-08)
Section