lan9420 Standard Microsystems Corp., lan9420 Datasheet - Page 96

• Manufacturer Part Number: lan9420
• Description: Lan9420/lan9420i Single-chip Ethernet Controller With Hp Auto-mdix Support And Pci Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.1 (03-31-08)
4.2.8
31:28
26:25
BITS
24:0
27
RESERVED
TX FIFO Early Fill Enable (TX_FILL_EN)
Setting this bit to a 1 allows the TX FIFO in the MIL to begin filling with new
data after the Ethernet collision window has passed. This bit must be
cleared if the Late Collision Control (LCOLL) bit in the MAC control register
(MAC_CR[12]) is set.
RX/TX Arbitration Priority Select (CSR_RXTXWEIGHT)
This field selects the arbitration priority ratio for receive and transmit DMA
operations. This field has no effect unless the BAR bit in the BUS_MODE
DCSR is cleared.
RESERVED
Bus Master Bridge Configuration Register (BUS_CFG)
This register determines the bus arbitration characteristics for the RX and TX DMA engines.
Setting
------------------------------------------------
00b
01b
10b
11b
Offset:
Priority Ratio (RX:TX)
4:1
1:1
2:1
3:1
DESCRIPTION
00DCh
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
96
Size:
32 bits
TYPE
SMSC LAN9420/LAN9420i
R/W
R/W
RO
RO
DEFAULT
00b
Datasheet
0b
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