peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 25
peb2255
Manufacturer Part Number
peb2255
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB2255.pdf
(374 pages)
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2.2
•
•
Table 1
Pin No.
42...48
41…38
35…28
25…22
49
52
Data Sheet
Pin Definitions and Functions
Pin Definitions - Microprocessor Interface
Symbol
A0 … A6 I
D0…D3
D4…D11
D12..D15
ALE
CS
Input (I)
Output (O)
Supply (S)
I/O
I
I
Function
Address Bus
These inputs interface to seven bits of the
system’s address bus to select one of the
internal registers for read or write.
Data Bus
Bidirectional tristate data lines which interface
to the system’s data bus. Their configuration is
controlled by the level of pin DBW:
8-bit mode (DBW = 0): D0 … D7 are active.
D8 … D15 are in high impedance and have to
be connected to
16-bit mode (DBW = 1): D0 … D15 are active.
In case of byte transfers, the active half of the
bus is determined by A0 and BHE/BLE and the
selected bus interface mode (via pin IM). The
unused half is in high impedance state.
Address Latch Enable
A high on this line indicates an address on the
external address/data bus. The address
information provided on lines A0 … A6 is
internally latched with the falling edge of ALE.
This function allows the FALC
connected to a multiplexed address/data bus
directly. In this case, pins A0 … A6 must be
connected to the Data Bus pins externally. In
case of demultiplexed mode this pin has to be
connected to
Chip Select
A low signal selects the FALC
and write operations.
25
V
DD
V
or
DD
V
or
SS
V
directly.
SS
.
Pin Descriptions
FALC-LH V1.3
®
®
-LH to be
-LH for read
PEB 2255
2000-07
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