peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 281
peb2255
Manufacturer Part Number
peb2255
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB2255.pdf
(374 pages)
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AUTO…
FM1…0…
Framer Mode Register 5 (Read/Write)
Value after RESET: 00
SRS…
EIBR…
Note: Bit FMR1.SIGM has also to be set, if bit-robbing mode is to be used.
XLD…
Data Sheet
FMR5
SRS
7
0…
1…
Select Frame Mode
FM = 0: 12-frame multiframe format (F12, D3/4)
FM = 1: 4-frame multiframe format (F4)
FM = 2: 24-frame multiframe format (ESF)
FM = 3: 72-frame multiframe format (F72, remote switch mode)
Valid in F12/F72 frame format only
0…
1…
0…
1…
Transmit Line Loopback (LLB) Down Code
0…
1…
Enable Auto Resynchronization
Signaling Register SIze
Enable Internal Bit-Robbing Access
EIBR
H
The receiver does not resynchronize automatically. Starting a
new synchronization procedure is possible via the bits:
FMR0.EXLS or FMR0.FRS.
Auto-resynchronization is enabled.
Signaling access is done via registers RS/XS1...6
Signaling access is done via increased register bank RS/
XS1...12
Normal operation (no bit-robbing).
CAS Bit-robbing mode selected
Normal operation.
A one in this bit position causes the transmitter to replace
normal transmit data with the LLB down (deactivate) code
continuously until this bit is reset. The LLB down code is
optionally overwritten by the framing/DL/CRC bits. For correct
operation bit FMR5.XLU must be cleared
XLD
XLU
281
SRO
XTM
RTF
FALC-LH V1.3
T1/J1 Registers
0
PEB 2255
2000-07
(1F)
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