peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 90

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

4.4.3.7
Due to signaling procedures using the five S
CRC multiframe structure, three possibilities of access via the microprocessor are
implemented.
• The standard procedure allows reading/writing the S
• The advanced procedure, enabled via bit FMR1.ENSA, allows reading/writing the S
A transmit or receive multiframe begin interrupt (ISR0.RMB or ISR1.XMB) is provided.
Registers RSA4-8 contains the service word information of the previously received CRC-
multiframe or 8 doubleframes (bit slots 4-8 of every service word). These registers are
updated with every multiframe begin interrupt ISR0.RMB.
With the transmit multiframe begin an interrupt ISR1.XMB is generated and the contents
of this registers XSA4-8 are copied into shadow registers. The contents is subsequently
sent out in the service words of the next outgoing CRC multiframe (or every
doubleframes) if none of the time slot 0 transparent modes is enabled. The transmit
multiframe begin interrupt XMB request that these registers should be serviced. If
requests for new information is ignored, current contents is repeated.
• The extended access via the receive and transmit FIFOs of the signaling controller. In
SA6-Bit Detection according to ETS 300233
Four consecutive received SA6-bits are checked on the by ETS 300233 defined SA6-bit
combinations. The FALC
SA62, SA63,SA64 = 1000; 1010; 1100; 1110; 1111. All other possible 4-bit combinations
are grouped to status “X”.
A valid SA6-bit combination must occur three times in a row. The corresponding status
bit in register RSA6S is set. Register RSA6S is from type “Clear on Read”. With any
change of state of the SA6-bit combinations an interrupt status ISR0.SA6SC is
generated.
During the basic frame asynchronous state updating of register RSA6S and interrupt
status ISR0.SA6SC is disabled. In multiframe format the detection of the SA6-bit
combinations can be done either synchronous or asynchronous to the submultiframe
(FMR3.SA6SY). In synchronous detection mode updating of register RSA6S is done in
the multiframe synchronous state (FRS0.LMFA=0). In asynchronous detection mode
updating is independent to the multiframe synchronous state.
Data Sheet
further support. The S
bit registers RSA4 … 8, XSA4 … 8.
this mode it is possible to transmit/receive a HDLC frame or a transparent bit stream
in any combination of the S
the corresponding bits XC0.SA8E-4E/TSWM.TSA8-4 and resetting of registers TTR1-
4, RTR1-4 and FMR1.ENSA. The access to and from the FIFOs is supported by
ISR0.RME,RPF and ISR1.XPR,ALS.
S
a
- Bit Access (E1)
a
-bit information is updated every other frame.
®
-LH detects following fixed SA6-bit combinations: SA61,
a
bits. Enabling is done by setting of bit CCR1.EITS and
90
a
bits (S
a4
… S
a
-bit registers RSW, XSW without
a8
Functional Description E1
) of every other frame of the
FALC-LH V1.3
PEB 2255
2000-07
a
-