at89c5131 ATMEL Corporation, at89c5131 Datasheet - Page 66

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at89c5131

Manufacturer Part Number
at89c5131
Description
8-bit Flash Microcontroller With Full Speed Usb Device At89c5131
Manufacturer
ATMEL Corporation
Datasheet

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Serial I/O Port
Framing Error Detection
4136C–USB–04/05
The serial I/O port in the AT89C5131 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-
taneously and at different baud rates.
Serial I/O port includes the following enhancements:
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (see Figure 31).
Figure 31. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 57) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 32 and Figure 33).
Figure 32. UART Timings in Mode 1
Framing error detection
Automatic address recognition
SMOD0 = X
SMOD0 = 1
RXD
SM0/FE
FE
RI
SMOD1
SMOD0
SM1
Start
Bit
D0
SM2
-
D1
REN
Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1
SM0 to UART Mode Control (SMOD0 = 0)
POF
To UART Framing Error Control
D2
TB8
GF1
D3
Data Byte
RB8
GF0
D4
D5
PD
TI
D6
IDL
RI
D7
AT89C5131
SCON (98h)
PCON (87h)
Stop
Bit
65

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