sta002 STMicroelectronics, sta002 Datasheet

no-image

sta002

Manufacturer Part Number
sta002
Description
Starmano Channel Decoder
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STA002
Manufacturer:
ST
0
FRONT_END INTERFACE:
FORWARD ERROR CORRECTION:
BACK_END INTERFACE:
CONTROL:
January 2002
IF input carrier frequency: f = 1.84 MHz
Single internal 6 bit A/D converter
QPSK demodulation
Input symbol frequency: Fs = 1.84 Msymbols/s
Digital Nyquist root filter:
- roll-off value of 0.4
Digital carrier loop:
- on-chip quadrature demodulator and tracking
- lock detector
- C/N indicator
Digital timing recovery:
- internal timing error evaluation, filter and
Digital AGC:
- internal signal power estimation and filter
- output control signal for AGC (1 bit PWM)
Inner decoder:
- Viterbi soft decoder for convolutional codes,
Deinterleaver block
Outer decoder:
- Reed-Solomon decoder for 32 parity bytes;
- Block lengths: 255
- Energy dispersal descrambler
Broadcast Channel selection
Audio Service Component selection to MPEG
decoder
Service Component selection
I
2
loop
correction
constraint length M=7, Rate 1/2
correction of up to 16 byte errors
C serial Bus control interface
®
STARMAN
DECRYPTION:
DESCRIPTION
Designed for World Space satellites digital audio
receivers, the STA002 Digital Receiver Front-end
integrates all the blocks needed to demodulate
incoming digital satellite audio signals from the
tuner: analog to digital converter, QPSK demodu-
lator, signal power estimator, automatic gain con-
trol, Viterbi decoder, deinterleaver, Reed-Solo-
mon decoder and energy dispersal descrabler. Its
advanced error correction functions guarantees a
low error rate even with small low gain receiver
antennas.
Additional functions include the selection of
broadcast channel, service components and
audio components for source decoding:
- The MPEG Audio bitstream is provided at the
- The Broadcast Channel is provided to the serial
- The Service Component is provided at the SC
World Space encryption scheme is supported for
pay programs and paging.
serial audio output port.
data output port.
output interface.
WES scheme supported
CHANNEL DECODER
TQFP44
STA002
1/43

Related parts for sta002

sta002 Summary of contents

Page 1

... DECRYPTION: WES scheme supported DESCRIPTION Designed for World Space satellites digital audio receivers, the STA002 Digital Receiver Front-end integrates all the blocks needed to demodulate incoming digital satellite audio signals from the tuner: analog to digital converter, QPSK demodu- lator, signal power estimator, automatic gain con- trol, Viterbi decoder, deinterleaver, Reed-Solo- mon decoder and energy dispersal descrabler ...

Page 2

... STA002 Fig. 1: Channel Decoder Block Diagram LOCK AGC RXI A/D RNXI QPSK PLL/CLOCK M_CLK DISTRIBUTION FRAME SYNC. MICROPROCESSOR INTERFACE RESET INTR SCL SDA Fig. 2: Pin Connection TEST 1 AGC VDD A_VDD RXI NRXI A_GND GND M_CLK CLK_TEST TEST 2 2/43 TDM_CLK TDM FRAME CONTROLLER TDM ...

Page 3

... Broadcast Channel Clock Broadcast Channel Data Output Service Component Enable Service Component Clock Service Component Data Output Parameter Parameter STA002 PAD Description CMOS Input Pad Buffer with Pull-Down Test Pin CMOS 2mA Output Driver Analog Pad Buffer Analog Pad Buffer Analog Pad Buffer with Comparator ...

Page 4

... STA002 ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic Protection esd Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin ...

Page 5

... F 100nF 100nF 100nF D99AU1011 5mA 100pF 100 A 100 A 100pF STA002 TEST9 TEST8 TEST7 BCDIN TEST6 TEST5 TEST4 RESET SCL SDA TEST3 SCDI SCCK SEN BCDO BCCK BCSYNC SDI SCK SEN MINTR INTR AGC LOCK ...

Page 6

... STA002 includes the following functions: Microprocessor interface Data transmission from microcontroller to the de- vice takes place through the 2 wires (SDA and SCL) I2C bus interface. STA002 acts always as a slave in all its communications. Interface to the Front-end This block receives from the RF front-end the QPSK modulated signal, centered at 1 ...

Page 7

... SCL line is low. 1.2 DEVICE ADDRESSING To start communication between the master and the STA002, the master must initiate with a start condition. Following this the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode ...

Page 8

... This mode can be initiated with either a current address read or a random address read. How- ever in this case the master does acknowledge the data byte output and the STA002 continues to output the next byte in sequence. To terminate the stream of bytes the master does not acknowledge the last received byte, but termi- nates the transfer with a STOP condition ...

Page 9

... TEST PURPOSE 026H 38 TEST PURPOSE 027H 39 TEST PURPOSE 028H 40 TEST PURPOSE 029H 41 TEST PURPOSE Note 1: no acknowledge when data is not available Note 2: when updated all bytes must be written REGISTER NAME STA002 RESET TYPE VALUE ...

Page 10

... STA002 1.5.2 SCH Registers HEX_COD DEC_COD 02AH 42 TEST PURPOSE 02BH 43 TEST PURPOSE 02CH 44 TEST PURPOSE 02DH 45 TEST PURPOSE 02EH 46 TEST PURPOSE 02FH 47 TEST PURPOSE 030H 48 TEST PURPOSE 031H 49 TEST PURPOSE 032H 50 TEST PURPOSE 033H 51 TEST PURPOSE 034H 52 TEST PURPOSE 035H 53 TEST PURPOSE ...

Page 11

... FLAG 09AH 154 RFU 09BH 155 RFU 09CH 156 RFU 09DH 157 RFU 09EH 158 RFU 09FH 159 RFU Note 1: when updated all bytes must be written REGISTER NAME STA002 RESET TYPE VALUE R/W 10H R/W 90H R/W 06H R/W 01H R/W 00H R/W 7FH R/W 16H R/W 00H R/W 23H ...

Page 12

... STA002 1.5.4 SCH_MEM Registers HEX_COD DEC_COD 100H 256 SC1_LENGHT & SC1_TYPE 101H 257 SC1_EC & SC1_PT 102H 258 SC1_PT 103H 259 LANGUAGE 1 104H 260 SC2_LENGHT & SC2_TYPE 105H 261 SC2_EC & SC2_PT 106H 262 SC2_PT 107H 263 LANGUAGE 2 108H 264 SC3_LENGHT & SC3_TYPE ...

Page 13

... RESERVED 228H 552 RESERVED 229H 553 RESERVED 22AH 554 RESERVED 22BH 555 RESERVED 22CH 556 RESERVED 22DH 557 RESERVED Note: when updated all bytes must be written REGISTER NAME STA002 RESET TYPE VALUE R/W 4BH R/W 43H R/W 2AH R/W 23H R/W 00H R/W 13H R/W 06H R/W 00H R/W 00H ...

Page 14

... QPSK block. The IF input signal, centered at 1.84MHz, is over- sampled at a frequency F ck M_CLK/2 according to STA002 presettings. 2.1 PLL This fully integrated PLL includes the phase/fre- quency detector, the charge pump, the filter and 14/43 REGISTER NAME REGISTER NAME the VCO ...

Page 15

... SYMFREQ3 MSB b15 b14 b13 b12 b11 SYMFREQ2 MSB SYMFREQ1 This register is divided into three bytes. The LSB byte is named SYMFREQ1, the MSB is named SYMFREQ3. STA002 in the register LSB beta_tmg LSB LSB b18 b17 b16 LSB b10 ...

Page 16

... STA002 The 22 bits value to be written into this register is given by: F SYMFREQ INT for example if M_CLK = 39,02687179MHz, Fck = M_CLK/4 SYMFREQ = 790995 = (C11D3)HEX which is the Reset Value. 3.3.2 Loop equations This timing loop is a second order one. The natu- ral frequency and the damping factor may be cal- ...

Page 17

... Like the timing loop the carrier loop is a second 102 144 204 288 408 0.13 0.09 0.06 0.04 0.25 0.18 0.13 0.09 0.50 0.36 0.25 0.18 1.01 0.71 0.50 0.36 2.01 1.42 1.01 0.71 4.03 2.85 2.01 1.42 8.06 5.70 4.02 2. IFFREQ INT b21 b20 b19 b18 b13 b12 b11 b10 STA002 9 10 577 NA 0.03 0.06 0.13 0.25 0.50 1.01 2.01 HEX LSB b17 b16 LSB b9 b8 LSB b1 b0 17/43 ...

Page 18

... STA002 TABLE 2. Carrier loop parameters (m = 22; K beta_car 0 NA fn(KHz) alpha_car order system controlled by two parameters, al- pha-car and beta-car, contained CARFLTPAR register. The natural frequency and the damping factor are given in the following formulas ...

Page 19

... The parameter AGC1_BETA can only take values from When AGC1_BETA is set to "111" the loop gain is null. This condition is useful to open the AGC1 loop. : 01H 06H given by: AGC1 AGC1_BETA AGC1 STA002 LSB b9 b8 LSB b1 b0 LSB b1 b0 19/43 ...

Page 20

... STA002 AGC1 integrator value register (AGC1_INTG) Internal address Reset Value: 00H MSB signed number To open the AGC1 loop this register must be re- set and the AGC1_BETA parameter must be "111". 3.6. AGC2 3.6.1 AGC2 control The AGC2 loop is used at the output of the Nyquist / interpolator filter for power optimization in the signal bandwith ...

Page 21

... PFDTHR CNTHR STA002 26 193 192 190 186 184 180 177 174 170 165 161 158 154 149 144 141 137 131 LSB X X LSB 21/43 ...

Page 22

... STA002 This register controls the Phase and frequency detector threshold (see par. 3.4.3) and the C/N indicator (see 3.8.2) FLAG REGISTER internal address LOCK CNFLAG reserved This is a read only register when the LOCK bit is 0 then the carrier is locked. When the CNFLAG bit is 1 then the C/N estimation is available ...

Page 23

... STA002 LSB b1 b0 LSB b1 b0 LSB b1 b0 23/43 ...

Page 24

... STA002 Reg name: PRC_MAXDELAY Internal address: 206 H Type: R/W Reset Value:06H MSB Description: Maximum accepted number of de- lay symbols among the prime rate channels be- longing to the same broadcast channel. Reg name: SP_TRSH2 Internal address: 205 H Type: R/W Reset Value: 13H MSB ...

Page 25

... MFP lock b5 : SCCF available 5. VITERBI DECODER AND SYNCHRONIZATION A Viterbi decoder has been implemented in the STA002 in order to extract the most probable transmitted sequence using a trace back proce- dure. This Viterbi decoder has been realized using 64- bit trace back depth and the soft decision ap- proach on the six-bit I and Q components coming from the QPSK demodulator ...

Page 26

... STA002 6. REED SOLOMON DECODER The STA 002 performs a real time block decoding operation both on the Time Slot Control Channel (TSCC) field and on the Broadcast Channel (BC) stream by means of a programmable Reed-Solo- mon (RS) decoder. This decoder works on blocks of 255 words of 8 bit symbols where the first 223 words represent the information and the last 32 the code redun- dancy ...

Page 27

... ADF2 multiframe start flag (SF field in the SCH) 1: first segment of multiframe or no multiframe 0: intermediate segment of multiframe indicate the segment offset and lenght field (SFT field in the SCH SOLF con- tains the total number of multiframe segments minus 1. STA002 ...

Page 28

... STA002 0000: one segment multiframe 0001: two segment multiframe ................................................. 1111: 16 segment multiframe SOLF contains the segment offset. Reg name: ADF1_REG Internal address: 006H, 005H Type: R ADF1 (15:8) ( addr 006H) MSB b15 b14 b13 b12 b11 ADF1 (7:0) ( addr 005H) MSB ...

Page 29

... Reg name: BCIN_DELAY_REG Internal address: 01BH Type: R/W LSB Default 00H MSB b7 Description : BC input delay and BC input enable register b0: enables external BC input b13 b12 b11 b10 STA002 LSB b1 b0 LSB b9 b8 LSB b1 b0 LSB b1 b0 29/43 ...

Page 30

... STA002 BC input delay (bytes) b2b1 = b3: Test purpose (must be set functional mode b4: test purpose Reg name: BC_ALARM_REG Internal address: 01CH Type: R/W Default:20H MSB Description: BC finite state machine control regis- ter (see table 6) b5 indicates the BC synchronization mode ...

Page 31

... RFU b23 = Encryption flag 0: not encrypted SC 1: encrypted SC b22 Program type language b29 b28 b27 b26 b21 b20 b19 b18 b13 b12 b11 b10 STA002 LSB b25 b24 LSB b17 b16 LSB b9 b8 LSB b1 b0 31/43 ...

Page 32

... STA002 Reg name: SERVICE COMPONENT 3 Internal address: 108H, 109H, 10AH, 10BH Type: R Description : Contains information about the service compo- nent of the broadcast channel SC3_LENGHT & SC3_TYPE (addr 108H) MSB b31 b30 b29 b28 b27 SC3 _EC & SC3_PT(addr 109H) MSB b23 ...

Page 33

... RFU b23 = Encryption flag 0: not encrypted SC 1: encrypted SC b22 Program type language b29 b28 b27 b26 b21 b20 b19 b18 b13 b12 b11 b10 STA002 LSB b25 b24 LSB b17 b16 LSB b9 b8 LSB b1 b0 33/43 ...

Page 34

... STA002 Reg name: SERVICE COMPONENT 7 Internal address: 118H, 119H, 11AH, 11BH Type: R Description : Contains information about the service compo- nent of the broadcast channel SC7_LENGHT & SC7_TYPE (addr 118H) MSB b31 b30 b29 b28 b27 SC7 _EC & SC7_PT(addr 119H) MSB b23 ...

Page 35

... The input delay is programmable via I2C bus with the BCIN_DELAY_REG register (01BH). 8.3 SERVICE COMPONENT INTERFACES The STA002 provides two service component in- terfaces which support the same protocol DATA INTERFACE (SCEN, SCDO, SCCK) - SOURCE DECODER INTERFACE (SEN, SDO, SCK) The service component interfaces consists of 3 wires each ...

Page 36

... STA002 Fig. 8: Format Of The Service Component Interface t clk SCCK/SCK SCDO/SDO SCEN/SEN t clk-off < 15ms t clk ~ 6.5 s CHANNEL DECODER INTERFACES BLOCK DIAGRAM RXI RNXI RF FRONT M_CLK END AGC LOCK SCCK SCDO 36/43 t clk-off IIC SCL SDA ...

Page 37

... MFP DATA MULTIPLEX DATA MULTIPLEX TSCC SYNC TSCC TSCC TSCC MFP MFP DATA READ DATA READ FIELD FIELD FIELD VER VER DATA FIELD PRCP SYNC SP DATA FIELD DECODED BC FRAME 432 ms DATA FIELD PRE SYNC SYNC HW syn is achievable STA002 DATA READ SP SYNC 37/43 ...

Page 38

... STA002 SCH & SCCF INTERRUPT BC FRAME 432 ms 20 bit DATA MULTIPLEX SP SCH DATA MULTIPLEX SP SCH Tx SP PRE SYNC DETECTION SP DETECTION DATA FIELD SP BRI EC ACI1 ACI2 Service Component multiplex SCCF interrupt SCH interrupt SCCF available Tm SCH available Tm = SCCF/ SCH not available setup ~ 32 ms Tsch = SCH interrupt time ~ 1 3 ...

Page 39

... CMOS Input Pad Buffer with Active Pull-Up / Pin number 20 A OUTPUT PIN Z D98AU920 IO INPUT PIN CAPACITANCE IO D98AU921 INPUT PIN Z D98AU923 Z INPUT PIN D98AU923 OUTPUT PIN Z D98AU906 OUTPUT PIN Z D98AU907 STA002 MAX LOAD Z 50pF OUTPUT PIN LOAD 5pF IO 100pF CAPACITANCE A 3.5pF CAPACITANCE A 3.5pF CAPACITANCE A 3.5pF CAPACITANCE A 3 ...

Page 40

... STA002 I/O CELL DESCRIPTION (Continued) 7) Analog Pad Buffer / Pins number M_CKL Input Stage / Pin number 9 A D98AU925 9) RXI/NRXI Input Stage / Pins number D98AU926 40/43 Z D98AU924 V REF Z RXI NRXI Z RXI NRXI Z RXI NRXI OUTPUT PIN CAPACITANCE A 4pF OUTPUT PIN TOTAL CAPACITANCE ...

Page 41

... C8H 00H 00H 05H 05H D3H 00H 11H 00H 0CH 10H 44H 44H 22H 22H 37H 00H 1DH 00H C1H 00H 00H 01H 20H 20H 3CH 3CH 3CH 3CH 20H 20H 20H 20H 00H 01H 06H 06H 02H 02H STA002 Note 1 2 41/43 ...

Page 42

... STA002 42/43 ...

Page 43

... Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States Standard Specifications as defined by Philips trademark of World-Space International Network Inc. STMicroelectronics GROUP OF COMPANIES http://www.st.com STA002 2 C Patent Rights to use these components 43/43 ...

Related keywords