sta335bw STMicroelectronics, sta335bw Datasheet

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sta335bw

Manufacturer Part Number
sta335bw
Description
2.1 Channels High Efficiency Digital Audio System
Manufacturer
STMicroelectronics
Datasheet

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Features
Order codes
December 2006
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Wide supply voltage range (5 to 24V)
4 Power Output Configurations
– 2 channels of ternary PWM (stereo mode)
– 3 channels - left, right using binary and LFE
– 1 channel PWM output (parallel-mode)
– 2 channels of ternary PWM (2 x 20 W) +
2.1 Channels of 24-Bit DDX
>94dB SNR and Dynamic Range
Selectable 32 KHz to 192 KHz Input Sample
Rates
I
Digital Gain/Attenuation +48 dB to -80 dB in
0.5 dB steps
Soft Volume Update
Individual Channel and Master
Gain/Attenuation
Dual Independent Limiters/Compressors
Dynamic Range Compression or Anti-Clipping
Modes
Automodes
– 15 Preset Crossover filters
– 2 Preset Anti-Clipping Modes
– Preset Nighttime Listening Mode
Individual Channel and Master Soft and Hard
Mute
Independent Channel Volume and DSP
Bypass
2
C control with Selectable Device Address
(2 x 20 W @ 8 Ω , 18 V)
using ternary PWM (2.1 mode) (2x10W +
1x20 W @ 2 x 4 Ω , 1 x 8 Ω, 20 V)
(1 x 40 W)
stereo lineout ternary
Part number
STA335BW
TM
2.1 channels high efficiency digital audio system
®
Temp range, ° C
0 to 150
Rev 1
PowerSSO36 Slug Down
Automatic Zero-Detect Mute
Automatic Invalid Input Detect Mute
2-Channel I
Input and Output Channel Mapping
4 x 28-bit User Programmable Biquads (EQ)
per channel
Bass/Treble Tone Control
DC Blocking Selectable High-Pass Filter
Selectable De-emphasis
Sub Channel Mix into Left and Right Channels
Advanced AM Interference Frequency
Switching and Noise Suppression Modes
Selectable High or Low Bandwidth Noise
Shaping Topologies
Variable Max Power Correction for lower full-
power THD
Selectable Clock Input Ratio
96 KHz Internal Processing Sample Rate, 24 to
28-bit precision
Thermal Overload and Short-circuit Protection
embedded
Video Application: 576 x fs input mode
supporting
PSSO-36 Slug Down package.
Package
2
S Input Data Interface
PowerSSO36
Slug Down
STA335BW
Packing
Tube
Preliminary Data
www.st.com
1/54
1

Related parts for sta335bw

sta335bw Summary of contents

Page 1

... Thermal Overload and Short-circuit Protection embedded ■ Video Application: 576 x fs input mode supporting ■ PSSO-36 Slug Down package. Temp range, ° 150 PowerSSO36 Slug Down Rev 1 STA335BW Preliminary Data PowerSSO36 Slug Down 2 S Input Data Interface Package Packing Tube 1/54 www.st.com ...

Page 2

... Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 2/54 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STA335BW ...

Page 3

... STA335BW 5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Configuration register A (address 0x00 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.2 Configuration register B (address 0x01 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 Configuration register C (Address 0x02 5.3.1 5.3.2 5.3.3 5.4 Configuration register D (address 0x03 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 Configuration register E (address 0x04 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial audio input interface format ...

Page 4

... AutoMode register 2 (address 0x0C interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STA335BW ...

Page 5

... STA335BW 5.12 User-defined coefficient control registers (addresses 0x16 to 0x26 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.12.8 5.12.9 5.12.10 Coefficient a1 data register bits 7.. 5.12.11 Coefficient a2 data register bits 23.. 5.12.12 Coefficient a2 data register bits 15.. 5.12.13 Coefficient a2 data register bits 7.. 5.12.14 Coefficient b0 data register bits 23.. 5.12.15 Coefficient b0 data register bits 15.. 5.12.16 Coefficient b0 data register bits 7.. 5.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.12.18 User-defined ...

Page 6

... Limiter attack threshold as a function of LxAT bits (DRC-Mode Table 28. Limiter release threshold function of LxRT bits (DRC-Mode).. . . . . . . . . . . . . . . 42 Table 29. RAM block for biquads, mixing, scaling and bass management Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6/54 = 25° 8Ω unless otherwise specified amb L STA335BW ...

Page 7

... STA335BW List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Pin connection PowerSSO-36 (Top view Figure 3. Test circuit Figure 4. Test circuit Figure 5. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Read mode sequence Figure 7. OCFG = 00 (default value Figure 8. OCFG = Figure 9. OCFG = Figure 10. OCFG = Figure 11 ...

Page 8

... Two channels can be provided by two full-bridges, providing power. The IC can also be configured as a 2.1 channels with provided by the device and external power for DDX® power drive. Also provided in the STA335BW are a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. Automodes™ ...

Page 9

... STA335BW 2 Connection diagram and pin description 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (Top view) GND_SUB TEST MODE VCC_REG GND_REG CONFIG OUT3B/DDX3B OUT3A/DDX3A 2.2 Pin description Table 1. Pin description Pin VSS OUT2B 7 GND2 ...

Page 10

... SDA I I SCL I I/O GND_DIG Digital Ground I/O Vdd_DIG Digital Supply Parameter (1) Description 2 S Serial Clock 2 S Left/Right Clock 2 S Serial Data Channels 1 and Serial Data 2 C Serial Clock Min. Typ. Max. 1.5 150 130 25 for details. STA335BW Unit °C/W °C °C °C ...

Page 11

... STA335BW 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V Power supply voltage (VCCxA, VCCxB) cc Vdd Logic Input Interface T Operating junction temperature op T Storage temperature stg 3.2 Recommended operating condition Table 4. Recommended operating condition Symbol V Power supply voltage (VCCxA, VCCxB) cc Vdd ...

Page 12

... Vrms RIPPLE Audio Input = Dither Only DDX Stereo Mode, Po KHz Stereo DDX Mode, <5 KHz One Channel Driven @ 1 W Other Channel Measured Ω Ω, 8 Ω) STA335BW Min. Typ. Max. Unit 0 ...

Page 13

... STA335BW 3.4 Testing 3.4.1 Functional pin status Table 6. Functional pin status Pin name Pin # PWRDN 23 PWRDN 23 TWARN 20 TWARN 20 EAPD 19 EAPD 19 Figure 3. Test circuit 1 Duty cycle = 50% Figure 4. Test circuit 2 Duty cycle=A M58 DTin(A) INA M57 Logic value 0 Low Absorption 1 Normal Operation From external power stage is indicated a Temperature 0 Warning ...

Page 14

... SA port configuration, 0x38 when and 0x3A when The eighth bit (LSB) identifies read or write operation RW, this bit is set read mode and 0 for write mode. After a START condition the STA335BW identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time ...

Page 15

... Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA335BW acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA335BW again responds with an acknowledgement. ...

Page 16

... DEV-ADDR DATA DATA CURRENT READ START ACK ACK SEQUENTIAL DEV-ADDR SUB-ADDR DEV-ADDR RANDOM READ START RW START 16/54 ACK DATA IN STOP ACK ACK DATA IN DATA IN STOP ACK NO ACK DATA RW STOP ACK NO ACK DATA STOP ACK ACK ACK NO ACK DATA DATA DATA RW STOP STA335BW ...

Page 17

... STA335BW 5 Register description Table 7. Register summary Addr Name D7 0x00 ConfA FDRB 0x01 ConfB C2IM 0x02 ConfC OCRB 0x03 ConfD MME 0x04 ConfE SVE 0x05 ConfF EAPD 0x06 Mute/LOC LOC1 0x07 Mvol MV7 0x08 C1Vol C1V7 0x09 C2Vol C2V7 0x0A C3Vol C3V7 ...

Page 18

... R/W 0 R/W 1 R/W 2 R/W The STA335BW supports sample rates of 32 KHz, 44.1 KHz, 48 KHz, 88.2 KHz, 96 KHz, 176.4 KHz, and 192 KHz. Therefore the internal clock is: ● 32.768 MHz for 32 KHz ● 45.1584 MHz for 44.1 KHz, 88.2 KHz, and 176.4 KHz ● 49.152 MHz for 48 KHz, 96 KHz, and 192 KHz ...

Page 19

... Bit R/W 4..3 R/W The STA335BW has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2 times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 9. ...

Page 20

... R/W 6 R/W The on-chip STA335BW power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces output limit (determined by TWOCL in Coeff RAM) to the modulation limit in an attempt to eliminate the thermal warning condition ...

Page 21

... Serial data interface The STA335BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA335BW always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12 ...

Page 22

... LSB first I 0001 1 Left-justified 24-bit data 0101 1 Left-justified 20-bit data 1001 1 Left-justified 18-bit data 1101 1 Left-justified 16-bit data 0010 1 Right-justified 24-bit data 0110 1 Right-justified 20-bit data 1010 1 Right-justified 18-bit data 1110 1 Right-justified 16-bit data STA335BW Interface Format Interface Format 2 S 16-bit data ...

Page 23

... STA335BW Table 11. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued) BICKI 64fs 5.2.4 Delay serial clock enable Bit R/W 5 R/W 5.2.5 Channel input mapping Bit R/W 6 R/W 7 R/W Each channel received via I Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I channel ...

Page 24

... DDX compensating pulse from 0 clock 1 CSZ2 ticks to 15 clock periods. 0 CSZ3 Compensating Pulse Size tick) compensating pulse size tick) clock period compensating pulse size … 300 ns (15 tick) clock period compensating pulse size CSZ1 CSZ0 OM1 Description Description STA335BW D0 OM0 1 ...

Page 25

... High-pass filter bypass Bit R/W 0 R/W The STA335BW features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB=0, this filter is enabled. 5.4.2 De-emphasis Bit R/W 1 ...

Page 26

... Each channel uses coefficient values 0 BQL 1 – Each channel uses channel 1 coefficient values RST Name 0 – Limiters act in anti-clipping mode 0 DRC 1 – Limiters act in dynamic range compression mode RST Name 1 ZDE Setting of 1 enables the automatic zero-detect mute STA335BW Description Description Description Description ...

Page 27

... STA335BW TM 5.4.8 Miami Mode Bit R/W 7 R/W 5.5 Configuration register E (address 0x04 SVE ZCE 1 1 5.5.1 Max power correction variable Bit R/W 0 R/W 5.5.2 Max power correction Bit R/W 1 R/W Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD full DDX system at maximum power output and slightly below ...

Page 28

... RST 3 R/W STA335BW features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~ this mode, which is still greater than the SNR of AM radio. ...

Page 29

... STA335BW 5.6 Configuration register F (address 0x05 EAPD PWDN 0 1 5.6.1 Output configuration Bit R/W 0 R/W 1 R/W Table 14. Output configuration engine selection OCFG(1..0) 2 Channel (Full-Bridge) Power, 2 Channel Data-Out: 1A/1B → 1A/1B 2A/2B → 2A/2B 00 LineOut1 → 3A/3B LineOut2 → 4A/4B Line Out Configuration determined by LOC register 2(Half-Bridge).1(Full-Bridge) On-Board Power: 1A → → ...

Page 30

... Channel 2 LineOut 1 LPF LineOut 2 LPF Figure 10. OCFG = 11 Channel 1 Channel 2 Power Channel 3 Device RST Name Setting of 1 enables the automatic invalid input 1 IDE detect mute STA335BW OCFG = 01 Half Channel 1 Bridge OUT1A Half Channel 2 Bridge OUT1B OUT2A Half Bridge Channel 3 Half Bridge OUT2B ...

Page 31

... STA335BW 5.6.3 Binary output mode clock loss detection Bit R/W 3 R/W Detects loss of input MCLK in binary mode and will output 50% duty cycle. 5.6.4 LRCK double trigger protection Bit R/W 4 R/W Actively prevents double trigger of LRCLK. 5.6.5 Auto EAPD on clock loss Bit R/W 5 R/W When active, issues a power device power down signal (EAPD) on clock loss detection. ...

Page 32

... MV4 C1V5 C1V4 C2V5 C2V4 C3M C2M C1M MV3 MV2 MV1 C1V3 C1V2 C1V1 C2V3 C2V2 C2V1 STA335BW D0 MMUTE 0 D0 MV0 1 D0 C1V0 0 D0 C2V0 0 ...

Page 33

... C3V7 C3V6 0 1 The Volume structure of the STA335BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -80 dB example if C3V = 0x00 or +48 dB and MV = 0x18 or –12 dB, then the total gain for channel 3 = +36 dB ...

Page 34

... Hard channel mute Hard channel mute AMGC1 AMGC2 0 0 User programmable clipping 2.1 AC limited clipping (10%) 2.1 DRC nighttime listening mode 2 XO1 XO0 AMAM2 STA335BW Volume -0.5 dB … -59.5 dB -60 dB -61 dB -62 dB … -80 dB … Mode AMAM1 AMAM0 AMAME ...

Page 35

... STA335BW 5.8.3 AM interference frequency switching Bit R/W 0 R/W Table 18. AutoMode AM switching frequency selection AMAM(2..0) 000 001 010 011 100 101 110 5.8.4 Bass management crossover Bit R/W 4 R/W 5 R/W 6 R/W 7 R/W Table 19. Bass management crossover frequency XO(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 RST Name AutoMode AM Enable 0 – ...

Page 36

... Crossover frequency 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 C1LS1 C1LS0 C2LS1 C2LS0 C3LS1 C3LS0 C1BO C1VPB C1EQBP C2BO C2VPB C2EQBP C3BO C3VPB 0 0 STA335BW D0 C1TCB 0 D0 C2TCB 0 D0 ...

Page 37

... STA335BW 5.9.3 Volume bypass Each channel contains an individual channel volume bypass particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel ...

Page 38

... L1A0 L1AT1 L1AT0 L1RT3 BTC3 BTC2 BTC1 Boost/Cut -12 dB -12 dB … … +12 dB + L1R3 L1R2 L1R1 L1RT2 L1RT1 STA335BW D0 BTC0 1 D0 L1R0 0 D0 L1RT0 1 ...

Page 39

... L2AT2 0 1 The STA335BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration Register F, bit 0 address 0x05 ...

Page 40

... LxR bits LxR(3..0) 0000 Fast 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Slow 1111 STA335BW Release Rate dB/ms 0.5116 Fast 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 Slow 0.0104 ...

Page 41

... STA335BW Anti-clipping mode Table 25. Limiter attack threshold as a function of LxAT bits (AC-Mode). LxAT(3..0) AC(dB relative to FS) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 Table 26. LxRT(3..0) 0 Register description Limiter release threshold as a function of LxRT bits (AC-Mode) ...

Page 42

... CFA5 CFA4 CFA3 C1B21 C1B20 C1B19 STA335BW Limiter release threshold function of LxRT bits (DRC-Mode). DRC(db relative to Volume + LxAT) -∞ -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB -15 dB -12 dB ...

Page 43

... STA335BW 5.12.3 Coefficient b1 data register bits 15.. C1B15 C1B14 0 5.12.4 Coefficient b1 data register bits 7.. C1B7 C1B6 0 0 5.12.5 Coefficient b2 data register bits 23.. C2B23 C2B22 0 0 5.12.6 Coefficient b2 data register bits 15.. C2B15 C2B14 0 5.12.7 Coefficient b2 data register bits 7.. C2B7 C2B6 0 0 5.12.8 Coefficient a1 data register bits 23..16 ...

Page 44

... D2 D1 C3B3 C3B2 C3B1 C4B19 C4B18 C4B17 C4B11 C4B10 C4B9 C4B3 C4B2 C4B1 C5B19 C5B18 C5B17 STA335BW D0 C3B8 0 D0 C3B0 0 D0 C4B16 0 D0 C4B8 0 D0 C4B0 0 D0 C5B16 0 ...

Page 45

... D6 Coefficients for user-defined EQ, Mixing, Scaling, and Bass Management are handled internally in the STA335BW via RAM. Access to this RAM is available to the user via an I register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...

Page 46

... When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example 10, 20, 35 decimal), and the STA335BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. 46/ address 0x1E ...

Page 47

... STA335BW 5.12.18 User-defined EQ The STA335BW provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2(b /2)X[ where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0 ...

Page 48

... Register description 5.12.21 Over-current post-scale The STA335BW provides a simple mechanism for reacting to over-current detection in the power-block. When the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides output attenuation when ocwarn is asserted. ...

Page 49

... STA335BW Table 29. RAM block for biquads, mixing, scaling and bass management (continued) Index (Decimal) Index (Hex) 54 0x36 55 0x37 56 0x38 57 0x39 58 0x3A 59 0x3B 60 0x3C 61 0x3D 62 0x3E 63 0x3F 5.13 Variable max power correction registers (addresses 0x27 to 0x28) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1 ...

Page 50

... D5 D4 FDRC13 FDRC12 FDRC5 FDRC4 UVFAULT OVFAULT OCFAULT DCC3 DCC2 DCC1 FDRC11 FDRC10 FDRC9 FDRC3 FDRC2 FDRC1 OCWARN TFAULT STA335BW D0 DCC0 1 D0 FDRC8 0 D0 FDRC0 0 D0 TWARN ...

Page 51

... The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA335BW is Ω Ω Ω Ω ...

Page 52

... G LEAD COPLANARITY 0 STA335BW ® OUTLINE AND MECHANICAL DATA PowerSSO-36 (slug-down) hx45û BOTTOM VIEW 7587131 A ...

Page 53

... STA335BW 8 Revision history Table 30. Document revision history Date 20-Dec-2006 Revision 1 Initial release. Revision history Changes 53/54 ...

Page 54

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 54/54 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA335BW ...

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