sta333bwqs13tr STMicroelectronics, sta333bwqs13tr Datasheet
sta333bwqs13tr
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sta333bwqs13tr Summary of contents
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... Individual channel and master soft and hard mute ! Independent channel volume and DSP bypass ! Automatic zero-detect mute Table 1. Device summary Order codes STA333BWQS STA333BWQS13TR March 2008 2.1-channel high-efficiency digital audio system ! Automatic invalid input detect mute ! 2-channel I ! Input and output channel mapping ® ...
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Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA333BWQS 5.4.4 5.4.5 5.4.6 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.5.7 6.5.8 6.6 Configuration register F (0x05 ...
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STA333BWQS 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 Coefficient a1 data register bits 7 ...
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Contents 11 License information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA333BWQS Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 53. Master volume offset as a function of MV[7: ...
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STA333BWQS Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview 1 Overview The STA333BWQS is an integrated circuit comprising digital audio processing, digital amplifier control, DDX ® single-chip DDX The STA333BWQS is part of the SoundTerminal streaming to the speaker, thereby offering cost effectiveness, low power dissipation and sound ...
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STA333BWQS Figure 1. Block diagram interface Volume control PLL Digital (DSP Protection current/thermal Logic Power control DDX Regulators Bias Overview Channel 1A Channel 1B Channel 2A Channel 2B Power 11/71 ...
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Connections and pin description 2 Connections and pin description 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (Top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B/DDX3B OUT3A/DDX3A 2.2 Pin description Table 2. Pin description Pin ...
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STA333BWQS Table 2. Pin description (continued) Pin Type Name Power VCC1 GND GND1 I/O ...
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Connections and pin description 2.3 Thermal data Table 3. Thermal data R Thermal resistance junction-case (thermal pad) th j-case T Thermal shut-down junction temperature th-sdj T Thermal warning temperature th-w T Thermal shut-down hysteresis th-sdh R Thermal resistance junction-ambient th ...
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STA333BWQS 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V Power supply voltage (VCC1, VCC2) cc VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage T Operating junction temperature op T Storage temperature stg Note: Stresses ...
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Electrical specifications 3.3 Electrical specifications - digital section Table 6. Electrical characteristics - digital section Symbol Parameter Low level input current , no pull- resistor High level input current, no pull-down I ih resistor V Low level input ...
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STA333BWQS Table 7. Electrical characteristics - power section (continued) Symbol Parameter Supply current from Vcc in power down I VCC Supply current from Vcc in operation Supply current DDX processing I VDD (reference only) Ilim Overcurrent limit Isc Short circuit ...
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Electrical specifications 3.5 Power-on sequence Figure 3. Power-on sequence VCC VCC VDD_DIG VDD_DIG XTI XTI Reset Reset PWDN PWDN Referring to Figure mimimum time between XTI master clock stable and reset ...
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STA333BWQS Figure 4. Test circuit 1 Duty cycle = 50% Figure 5. Test circuit 2 Duty cycle=A M58 DTin(A) INA M57 Low-current dead time = MAX(DTr, DTf) +Vcc M58 OUTxY INxY M57 gnd High Current Dead time for Bridge application ...
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Processing data paths 4 Processing data paths Here are some diagrams that represent the data processing paths inside STA333BWQS. The first 2-times oversampling FIR filter allows 2x fs audio processing. Then a selectable high-pass filter removes the DC level. Four ...
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STA333BWQS bus specification The STA333BWQS supports the I to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device ...
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I C bus specification 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BWQS acknowledges this and the writes for the byte of internal address. After ...
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STA333BWQS 5.4.5 Write mode sequence Figure 7. Write mode sequence BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START 5.4.6 Read mode sequence Figure 8. Read mode sequence ACK CURRENT DEV-ADDR ADDRESS READ START RW ACK RANDOM DEV-ADDR ADDRESS READ START ...
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Register description 6 Register description Table 9. Register summary Addr Name D7 0x00 ConfA FDRB 0x01 ConfB C2IM 0x02 ConfC OCRB 0x03 ConfD MME 0x04 ConfE SVE 0x05 ConfF EAPD 0x06 Mute/LOC LOC1 0x07 Mvol MV7 0x08 C1Vol C1V7 0x09 ...
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STA333BWQS Table 9. Register summary (continued) Addr Name D7 0x20 A2cf1 C4B23 0x21 A2cf2 C4B15 0x22 A2cf3 C4B7 0x23 B0cf1 C5B23 0x24 B0cf2 C5B15 0x25 B0cf3 C5B7 0x26 Cfud 0x27 MPCC1 MPCC15 MPCC14 0x28 MPCC2 MPCC7 0x29 DCC1 DCC15 0x2A ...
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Register description The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency ( The relationship between the input clock and the input sample rate is determined by both the MCSx ...
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STA333BWQS 6.1.3 Thermal warning recovery bypass Table 14. Thermal warning recovery bypass Bit R/W 5 R/W If the thermal warning adjustment is enabled (TWAB=0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal ...
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Register description 6.2 Configuration register B (0x01 C2IM C1IM 1 0 6.2.1 Serial audio input interface format Table 17. Serial audio input interface format Bit R/W 0 R/W 1 R/W 2 R/W 3 R/W 6.2.2 Serial data interface ...
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STA333BWQS Table 19. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI 32fs 48fs 64fs Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI 32fs 48fs SAI [3:0] SAIFB 2 0000 ...
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Register description Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued) BICKI 64fs 6.2.4 Delay serial clock enable Table 21. Delay serial clock enable Bit R/W 5 R/W 6.2.5 Channel input mapping Table 22. Channel input ...
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STA333BWQS 6.3 Configuration register C (0x02 OCRB 1 ® 6.3.1 DDX power output mode Table 23. DXX power output mode Bit R/W 0 R/W 1 R/W The DDX power output mode selects how the DDX output timing is ...
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Register description 6.3.3 Over-current warning detect adjustment bypass Table 27. Over-current warning detect adjustment bypass Bit R/W 7 R/W The OCWARN input is used to indicate an over-current warning condition. When OCWARN is asserted (set to 0), the power control ...
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STA333BWQS 6.4.3 DSP bypass Table 30. DSP bypass Bit R/W 2 R/W Setting the DSPB bit bypasses the EQ functionality of the STA333BWQS. 6.4.4 Post-scale link Table 31. Post-scale link Bit R/W 3 R/W Post-scale functionality can be used for ...
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Register description 6.4.7 Zero-detect mute enable Table 34. Zero-detect mute enable Bit R/W 6 R/W Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the ...
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STA333BWQS 6.5.3 Noise-shaper bandwidth selection Table 38. Noise-shaper bandwidth selection Bit R/W RST 2 R/W 6.5.4 AM mode enable Table 39. AM mode enable Bit R/W RST 3 R/W STA333BWQS features a DDX processing mode that minimizes the amount of ...
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Register description 6.5.8 Soft volume update enable Table 43. Soft volume update enable Bit R/W RST 7 R/W 6.6 Configuration register F (0x05 EAPD PWDN 0 6.6.1 Output configuration Table 44. Output configuration Bit R/W 0 R/W 1 ...
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STA333BWQS Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. Figure 9. OCFG = 00 (default value) ...
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Register description For each configuration the PWM from the digital driver are mapped in different way to the power stage: 2.0 channels, two full bridges (OCFG = 00) " DDX1A ' OUT1A " DDX1B ' OUT1B " DDX2A ' OUT2A ...
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STA333BWQS 2.1 channels, two half bridges + one full bridge (OCFG = 01) " DDX1A ' OUT1A " DDX2A ' OUT1B " DDX3A ' OUT2A " DDX3B ' OUT2B " DDX1A ' OUT3A " DDX1B ' OUT3B " DDX2A ' ...
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Register description 2.1 channels, two fullbridge + one external full bridge (OCFG = 10) " DDX1A ' OUT1A " DDX1B ' OUT1B " DDX2A ' OUT2A " DDX2B ' OUT2B " DDX3A ' OUT3A " DDX3B ' OUT3B " EAPD ...
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STA333BWQS 6.6.3 Binary output mode clock loss detection Table 47. Binary output mode clock loss detection Bit R/W 3 R/W Detects loss of input MCLK in binary mode and will output 50% duty cycle. 6.6.4 LRCK double trigger protection Table ...
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Register description 6.7 Volume control registers (0x06 to 0x0A) 6.7.1 Mute/line output configuration register D7 D6 LOC1 LOC0 0 0 Table 52. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this ...
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STA333BWQS The master mute, when set to 1, mutes all channels at once, whereas the individual channel mutes (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down ...
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Register description Table 54. Channel volume as a function of CxV CxV[7:0] … 11111111 (0xFF) 6.8 Auto mode registers (0x0B and 0x0C) 6.8.1 AutoMode register 1 (0x0B Table 55. AutoMode gain compression/limiters selection AMGC[1: ...
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STA333BWQS Table 57. AutoMode AM switching frequency selection (continued) AMAM[2:0] 101 110 6.8.4 Bass management crossover Table 58. Base management crossover Bit R/W 4 R/W 5 R/W 6 R/W 7 R/W Table 59. Bass management crossover frequency XO[3:0] 0000 0001 ...
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Register description 6.9 Channel configuration registers ( 0x0E to 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 6.9.1 Tone control bypass Tone control (bass/treble) can be bypassed on a ...
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STA333BWQS 6.9.5 Limiter select Limiter selection can be made on a per-channel basis according to the channel limiter select bits. . Table 60. Channel limiter mapping as a function of CxLS bits CxLS[1: 6.9.6 Output mapping Output ...
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Register description Table 62. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] 1101 1110 1111 6.11 Dynamics control registers (0x12 to 0x15) 6.11.1 Limiter 1 attack/release rate D7 D6 L1A3 L1A2 0 1 6.11.2 Limiter 1 ...
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STA333BWQS active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. ...
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Register description Table 63. Limiter attack rate as a function of LxA bits LxA[3:0] Attack Rate dB/ms 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 50/71 3.1584 Fast 2.7072 2.2560 1.8048 1.3536 ...
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STA333BWQS Anti-clipping mode Table 65. Limiter attack threshold as a function of LxAT bits (AC-Mode). LxAT[3:0] AC(dB relative to FS) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 66. LxRT[3:0] -12 ...
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Register description Dynamic range compression mode Table 67. Limiter attack threshold as a function of LxAT bits (DRC-Mode). LxAT[3:0] DRC(dB relative to Volume) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6.12 ...
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STA333BWQS 6.12.3 Coefficient b1 data register bits 15 C1B15 C1B14 0 0 6.12.4 Coefficient b1 data register bits 7 C1B7 C1B6 0 6.12.5 Coefficient b2 data register bits 23: C2B23 C2B22 0 0 6.12.6 ...
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Register description 6.12.10 Coefficient a1 data register bits 7 C3B7 C3B6 0 6.12.11 Coefficient a2 data register bits 23: C4B23 C4B22 0 0 6.12.12 Coefficient a2 data register bits 15 C4B15 C4B14 0 0 ...
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STA333BWQS 6.12.17 Coefficient write/read control register D7 D6 Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA333BWQS via RAM. Access to this RAM is available to the user via register ...
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Register description Writing a single coefficient to RAM 1. Write 6-bits of address Write top 8-bits of coefficient Write middle 8-bits of coefficient Write bottom 8-bits of coefficient ...
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STA333BWQS Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner: CxHy0 = CxHy1 = b 2 CxHy2 = -a 1 CxHy3 = -a 2 CxHy4 = where x represents ...
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Register description the over-current post-scale factor is set to applied, it remains until the device is reset. Table 69. RAM block for biquads, mixing, scaling, bass management Index (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 … 0x13 0x14 0x15 … ...
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STA333BWQS Table 69. RAM block for biquads, mixing, scaling, bass management (continued) Index (Hex) 0x3D 0x3E 0x3F 6.13 Variable max power correction registers (0x27 to 0x28) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is ...
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Register description 6.16 Device status register (0x2D PLLUL FAULT This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault ...
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STA333BWQS 7 Application 7.1 Application scheme for power supplies Here in the next figure the typical application scheme for STA333BWQS concerning the power supplies. A particular care has to be devoted to the layout of the PCB. In particular the ...
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Application 7.3 Typical output configuration Here after the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other possible output configuration recommended schematics. Figure 20. Output configuration for stereo BTL mode OUT1A ...
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STA333BWQS 8 Characterization data Figure 21. Output power (for 1% THD) Figure 22. FFT 0 dBfs (1 kHz ohm) +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - ...
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Characterization data Figure 23. FFT -60 dBfs (1 kHz ohm) +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 -80 A ...
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STA333BWQS Figure 25. FFT 0 dBfs (1 kHz ohm) +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 - ...
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Package thermal characteristics 9 Package thermal characteristics Using a double-layer PCB the thermal resistance junction to ambient with 2 copper ground area of 3x3 cm and with 16 via holes (see The dissipated power within the device depends primarily on ...
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STA333BWQS 10 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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... An independent license for such use is required and can be obtained by contacting the company or companies concerned. Once the license is obtained, a copy must be sent to STMicroelectronics. The details of all the features requiring licenses are not provided within the datasheet and register manual. They are provided only after a copy of the license has been received by STMicroelectronics ...
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... STA333BWQS 12 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. SoundTerminal is a trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. QHD and QXpander are registered trademarks of QSound Labs Inc. Trademarks and other acknowledgements 69/71 ...
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Revision history 13 Revision history Table 70. Document revision history Date 27-Mar-2008 70/71 Revision 1 Initial release STA333BWQS Changes ...
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... STA333BWQS Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...