sta323wqs STMicroelectronics, sta323wqs Datasheet
sta323wqs
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sta323wqs Summary of contents
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... Field proven stereo soundfield enhancement technology – Provides improved audio image width, seperation and depth for stereo signals – Synthesizes a 3D stereo soundfield Order codes Part number STA323WQS STA323WQS13TR Rev 1 Package PowerSO36 (Slug Down) PowerSO36 in tape & reel 1/72 www.st.com 1 ...
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... Block diagram and configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Output power against supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 4.1.2 4.1.3 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 STA323WQS I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.1 6.1.2 6.1.3 6.1.4 6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.1 6.3.2 6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4.1 6.4.2 6.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 ...
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... STA323WQS 7 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 Configuration register A (address 0x00 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 Configuration register B (address 0x01 7.2.1 7.3 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.1 7.4 Configuration register C (address 0x02 7.4.1 7.4.2 7.5 Configuration register D (address 0x03 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.6 Configuration register E (address 0x04 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 Configuration register F (address 0x05 7.7.1 7.8 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.8.1 7.8.2 7.8.3 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Thermal warning adjustment bypass ...
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... Coefficient b2 data register bits 7...0 (address 0x1C Coefficient a1 data register bits 23...16 (address 0x1D Coefficient a1 data register bits 15...8 (address 0x1E Coefficient a1 data register bits 7...0 (address 0x1F Coefficient a2 data register bits 23...16 (address 0x20 Coefficient a2 data register bits 15...8 (address 0x21 STA323WQS ...
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... STA323WQS 8.6.13 8.6.14 8.6.15 8.6.16 8.6.17 8.7 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.8 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.9 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.10 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.11 Variable max power correction (address 0x27-0x28 8.12 Fault detect recovery (address 0x2B - 0x2C 8.13 Status indicator register (address 0x2D 8.13.1 8.13.2 8.13.3 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10 License information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11 Revision history ...
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... A single, parallel, full-bridge channel capable of high-current operation and giving 1 x 40W output. The STA323WQS also provides a full set of digital processing features. These includes up to four programmable 28-bit biquads (EQ) per channel, and bass and treble tone control. Automodes™ enable a time-to-market advantage by substantially reducing the amount of software development needed for specific functions ...
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... STA323WQS 1.1 Block diagram and configurations Figure 1. Block diagram SDA SCL LRCKI Serial data input, channel BICKI mapping and resampling SDI_12 Power down Figure 2. Channel signal flow diagram through the digital core Channel input Re-sampling mapping 1.2 EQ processing Two channels of input data (re-sampled if necessary kHz are provided to the EQ processing block ...
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... Channel 1 Half bridge OUT1B OUT2A Half bridge Channel 2 Half bridge OUT2B OUT1A Half Channel 1 bridge Half bridge Channel 2 OUT1B OUT2A Half bridge Channel 3 Half bridge OUT2B OUT1A Half bridge Half bridge OUT1B Channel 3 OUT2A Half bridge Half bridge OUT2B STA323WQS ...
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... STA323WQS 2 Schematics Table 1. Component selection “Table A” - full-bridge operation Load 4 Ω 6 Ω 8 Ω Table 2. Component selection "Table B" - binary half-bridge operation Load 4 Ω 6 Ω 8 Ω Table 3. Component selection "Table C" - mono operation Load 2 Ω 3 Ω 4 Ω Inductor 10 µH 15 µH 22 µH Inductor 22 µ ...
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... Schematics Figure 7. Schematic for 2 (half-bridge) channels + 1 (full-bridge)-channel on-board Figure 8. Power schematic for 2 (full-bridge)-channel on-board power 10/72 STA323WQS ...
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... STA323WQS Figure 9. Power schematic for 1 mono parallel channel Figure 10. Pin layout (viewed from top of device) Table 4. Pin description Pin N. N. OUT2B N. GND2B GND2A OUT2A 9 28 OUT1B ...
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... Analog supply Analog supply 3.3 I SDI_12 I²S serial data channels 1 and 2 I/O LRCKI I²S left/right clock, I BICKI I²S serial clock I/O Digital ground Digital ground I/O Digital supply Digital supply 3.3 V I/O VSS digital 5 V regulator referred to +Vcc 5 V regulator referred to ground (signal positive I/O VCC digital supply) STA323WQS ...
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... STA323WQS Table 5. Absolute maximum ratings Symbol Parameter V 3.3 V I/O power supply DD_3.3 V Voltage on input pins i V Voltage on output pins o T Storage temperature stg T Ambient operating temperature amb V DC supply voltage CC V Maximum voltage on pins 20 MAX Table 6. Thermal data Symbol R Thermal resistance junction to case (thermal pad) ...
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... Leakage < 1µA Test condition IoI = 2mA Ioh = -2mA Parameter Test conditions Id=1 A dsON Vcc=35 V dss dsON Id=1 A dsON Id=1 A See test circuit no.1; see Figure 12 Resistive load Resistive load Resistive load Resistive load; as STA323WQS Min. Typ. Max. Unit µA 1 µA 2 µA 2 2000 V Min. Typ. Max. 0.8 2.0 0.4 0.15 VDD -0.15 = 3.3 V ...
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... STA323WQS Table 10. Power electrical characteristics (V unless otherwise specified) (continued) Symbol Supply voltage operating V CC voltage Low logical state voltage High logical state voltage Supply current from Vcc in VCC- PWRDN PWRDN Supply current from Vcc in I VCC-hiz Tri-state Supply current from Vcc in ...
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... The "time zero" reference point is taken where V Figure 12. Recommended power up and power down sequence 16/72 Low current dead time = MAX(DTr,DTf) +Vcc M58 OUTY INY M57 gnd crosses the under voltage lockout threshold. CC STA323WQS OUTY Vcc (3/4)Vcc (1/2)Vcc (1/4)Vcc t DTr DTf R 8Ω V67 = + - ...
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... DDX® mode or binary full bridge mode. Output power is constrained for higher impedance loads by the maximum voltage limit of the STA323WQS and by the over-current protection limit for lower impedance loads. The minimum threshold for the over-current protection circuit of the STA323WQS (at 25 º ...
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... Figure 15 shows the output power as a function of power supply voltages for loads and 8 Ω when the STA323WQS is operated in a half-bridge binary mode. The solid curves depict typical performance. Minimum current limit is not reached for these combinations of voltage and load impedance. The output power curves assume proper thermal management of the power device's internal dissipation ...
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... STA323WQS Figure 16. Half bridge binary mode output power vs. supply voltage (THD+N=1%). Curves taken at 1 kHz and using a 330µF blocking capacitor 4.1.1 Audio performance (operation with Vcc = Ohm load, stereo mode) Figure 17. Typical efficiency Figure 18. Typical frequency response ...
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... Audio performance - stereo mode (operation with Vcc = 18.5 V) Figure 21. Frequency response BTL, 8 ohm 20/ STA323WQS ...
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... STA323WQS Figure 22. Channel separation 1 W, BTL stereo mode Figure 23. THD vs. PWR BTL, 1 kHz Figure 24. THD vs. freq output, stereo mode Electrical characteristics curves ...
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... STA323WQS Figure 28. FFT 0 dbfs 1 kHz, 1 kHz 4 Ω Figure 29. FFT -60 dbfs 1 kHz, 8 Ω Figure 30. FFT -60 dbfs 1 kHz, 6 Ω Electrical characteristics curves ...
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... STA323WQS ...
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... STA323WQS Figure 34. Channel separation 1 W, half bridge binary Figure 35. THD+N vs. PWR SE, 1 kHz input frequency, half bridge binary Figure 36. THD+N vs. PWR SE, 1 kHz input frequency, half bridge binary Electrical characteristics curves ...
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... STA323WQS Figure 40. FFT kHz SE, 3 Ω Figure 41. FFT kHz SE, 4 Ω Figure 42. FFT - khz SE, 2 Ω Electrical characteristics curves ...
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... STA323WQS 5 Pin descriptions OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3) The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers. OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3) Driving RESET low sets all outputs low and returns all register settings to their defaults. The reset is asynchronous to the internal clock ...
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... Data input During the data input the STA323WQS samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. ...
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... After receiving, the internal byte address the STA323WQS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA323WQS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
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... STA323WQS I2C bus specification 6.5 Write mode sequence 2 Figure 46 write procedure BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START 6.6 Read mode sequence 2 Figure 47 read procedure ACK CURRENT DEV-ADDR ADDRESS READ START RW ACK RANDOM DEV-ADDR ADDRESS READ START RW RW= ACK HIGH ...
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... STA323WQS 7 Register descriptions Table 12. Register summary Address Name D7 0x00 ConfA FDRB 0x01 ConfB C2IM 0x02 ConfC 0x03 ConfD MME 0x04 ConfE SVE 0x05 ConfF EAPD 0x06 Mmute 0x07 Mvol MV7 0x08 C1Vol C1V7 0x09 C2Vol C2V7 0x0A C3Vol C3V7 0x0B Auto1 ...
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... R R/W 0 The STA323WQS supports sample rates of 32 kHz, 44.1 kHz, 48 khz, 88.2 kHz, and 96 kHz. Therefore the internal clock is: ● 32.768 MHz for 32 kHz ● 45.1584 MHz for 44.1 khz, 88.2 kHz, and 176.4 kHz ● 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...
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... R/W 4...3 R/W The STA323WQS has variable interpolation (re-sampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. The IR bits determine the re-sampling ratio of this interpolation. ...
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... R/W 1 The STA323WQS on-chip power output block provides feedback to the digital controller by the power control block inputs. The TWARN input is used to indicate a thermal warning condition. When TWARN is active (set to 0 for a period greater than 400 ms) the power control block forces an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition ...
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... Serial data interface The STA323WQS serial audio input interfaces with standard digital audio components and accepts several different serial data formats. The STA323WQS always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 33), serial clock BICKI (pin 31), and serial data 1 and 2 SDI12 (pin 32) ...
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... Register descriptions Table 22. lists the serial audio input formats supported by STA323WQS when BICKI = fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 kHz. Table 21. First bit selection table Note: Serial input and output formats are specified distinctly. Table 22. ...
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... STA323WQS Table 22. Supported serial audio input formats (continued) BICKI Table 23. Serial input data timing characteristics ( 192 kHz) BICKI frequency (slave mode) BICKI pulse width high (T1) (slave mode) BICKI active to LRCKI edge delay (T2) BICKI active to LRCKI edge delay (T3) SDI valid to BICKI active setup (T4) BICKI active to SDI hold time (T5) Figure 49 ...
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... Not used Recommended Variable compensation ® compensating pulse Compensating pulse size 0 clock period compensating pulse size 1 clock period compensating pulse size … 16 clock period compensating pulse size … 31 clock period compensating pulse size STA323WQS CSZ1 CSZ0 OM1 Description ® ...
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... By setting this bit to 1, de-emphasis is implemented on all channels. DSPB (DSP Bypass, Bit D2, CFA) bit must be set to 0 for de-emphasis to function. 7.5.3 DSP bypass Table 31. DSP bypass Bit R/W RST 2 R/W 0 Setting the DSPB bit bypasses all the EQ and mixing functionality of the STA323WQS core. 7.5.4 Post-scale link Table 32. Post-scale link Bit R/W RST 3 R ...
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... Name 0: each channel uses coefficient values BQL 1: each channel uses channel 1 coefficient values Name 0: limiters act in anti-clipping mode DRC 1: limiters act in dynamic range compression mode RST Name 1 ZDE Setting of 1 enables the automatic zero-detect mute STA323WQS Description Description Description ...
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... AM mode enable Bit R/W 3 R/W The STA323WQS features a DDX generated in the frequency range of AM radio. This mode is intended for use when DDX operating in a device with an active AM tuner. The SNR of the DDX to ~ this mode, which is still greater than the SNR of AM radio. D5 ...
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... R/W 7 R/W The STA323WQS includes a soft volume algorithm that steps through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE=0 this can be bypassed and volume changes will jump from the old to the new value directly. This feature is available only if individual channel volume bypass bit is set to 0. ...
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... STA323WQS 7.7 Configuration register F (address 0x05 EAPD PWDN 0 7.7.1 Output configuration selection Table 43. Output configuration selection Bit R/W 1…0 R/W Table 44. Output configuration selections OCFG (1... Table 45. Invalid input detect mute enable Bit R/W 2 R/W Setting the IDE bit enables this function, which looks at the input I automatically mutes all outputs if the signals are invalid ...
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... MV5 MV4 C1V5 C1V4 1 0 Description Description ® power device. This register has MV3 MV2 MV1 C1V3 C1V2 C1V1 STA323WQS D0 MMUTE 0 D0 MV0 1 D0 C1V0 0 ...
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... Volume description The volume structure of the STA323WQS consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed ...
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... Hard Master Mute Hard channel mute AMGC1 AMGC0 AMV1 Mode (Biquad 1-4) User Programmable Preset EQ – PEQ bits Auto Volume Controlled Loudness Curve Not used STA323WQS 0dB -0.5dB -1dB … -38dB … -127dB volume +48dB +47.5dB +47dB … +0.5dB 0dB -0.5dB … ...
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... STA323WQS Setting AMEQ to any value, other than 00, enables automode EQ. When set, biquads 1-4 are not user programmable. Any coefficient settings for these biquads is ignored. Also when automode EQ is used the pre-scale value for channels 1 and 2 becomes hard-set to –18 dB. Table 52. Automode volume AMV (1,0) ...
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... XO (3…0) Otherwise: preset coefficients are used for the required crossover setting Bass management - crossover frequency STA323WQS 44.1 kHz/88.2 kHz input Fs 1.181 MHz – 1.340 MHz 1.341 MHz – 1.500 MHz 1.501 MHz – 1.700 MHz ...
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... STA323WQS 7.9.2 Register - preset EQ settings (address 0x0D Table 59. Preset EQ selection PEQ (3..0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 D5 D4 ...
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... C1LS1 C1LS0 C2LS1 C2LS0 C3LS1 C3LS0 0 0 Setting Loudness 14 Loudness 15 Loudness 16 (most boost C1BO C1VBP C1EQBP C2BO C2VBP C2EQBP C3BO C3VBP 0 0 STA323WQS D0 C1TCB 0 D0 C2TCB 0 D0 ...
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... STA323WQS It is also possible to map each channel independently to either of the two limiters available within the STA323WQS. In the default mode the channels are not mapped to a limiter. Table 60. Channel Limiter Mapping Selection CxLS (1, Each PWM output channel can receive data from any channel output of the volume block. ...
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... Dynamics control description The STA323WQS includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in Configuration Register D, bit 5 address 0x03 ...
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... STA323WQS The release of limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume limiter block is passed through an RMS filter. The output of this filter is compared with the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register ...
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... Anti-clipping mode Table 65. Limiter attack - threshold selection (AC-mode) 56/72 Attack rate dB/ms Release rate dB/ms LxAT (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 STA323WQS 0.0501 0.0451 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 ...
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... STA323WQS Table 65. Limiter attack - threshold selection (AC-mode) (continued) . Table 66. Limiter release threshold selection (AC-mode) LxRT (3...0) 7.12.7 Dynamic range compression mode Table 67. Limiter attack - threshold selection (DRC-mode) LxAT (3...0) 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 ...
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... STA323WQS DRC (dB relative to volume) -19 -17 -16 -15 -14 -13 -12 - DRC (db relative to Volume + LxAT) -∞ -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB ...
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... Post-scale The STA323WQS provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. The post-scale block is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same ...
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... User-programmable settings 8.4 Mix/bass management The STA323WQS provides one post-EQ mixing block per channel. Each channel has two mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the two channels of input to the mixing block. These coefficients are accessible via the User Controlled Coefficient RAM described below ...
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... STA323WQS 8.5 Calculating 24-bit signed fractional numbers from a dB value The pre-scale, mixing, and post-scale functions of the STA323WQS use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from - possible to calculate the coefficient to use for a given negative dB value (attenuation) using the equations following. ● ...
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... D5 D4 C2B13 C2B12 C2B5 C2B4 C1B21 C1B20 C3B13 C3B12 C3B5 C3B4 0 0 STA323WQS C2B19 C2B18 C2B17 C2B11 C2B10 C2B9 C2B3 C2B2 C2B1 C1B19 ...
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... STA323WQS 8.6.11 Coefficient a2 data register bits 23...16 (address 0x20 C4B23 C4B22 0 0 8.6.12 Coefficient a2 data register bits 15...8 (address 0x21 C4B15 C4B14 0 8.6.13 Coefficient a2 data register bits 7...0 (address 0x22 C4B7 C4B6 0 0 8.6.14 Coefficient b0 data register bits 23...16 (address 0x23 ...
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... Coefficient write control register (address 0x26 Coefficients for EQ, Mix and Scaling are handled internally in the STA323WQS via RAM. Access to this RAM is available to the user via an I registers are dedicated to this function. The first register contains base address of the coefficient: five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the reading or writing of the coefficients to RAM ...
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... When using this technique, the 8-bit address specifies the address of the biquad b1 coefficient (for example 0, 5, 10, 15, …, 45 decimal), and the STA323WQS generates the RAM addresses as an offsets from this base value to write the complete set of coefficient data. ...
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... Channel 1 – mix 1 0x39 Channel 1 – mix 2 0x3A Channel 2 – mix 1 0x3B Channel 2 – mix 2 0x3C Channel 3 – mix 1 0x3D Channel 3 – mix 2 0x3E Unused 0x3F Unused STA323WQS Coefficient Default ... ... C1H44 0x400000 C2H10 0x000000 C2H11 0x000000 … … C2H44 0x400000 C12H0 (b1/2) ...
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... STA323WQS 8.11 Variable max power correction (address 0x27-0x28) The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = MPCC15 MPCC14 0 MPCC7 MPCC6 1 8.12 Fault detect recovery (address 0x2B - 0x2C) FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is active, the TRISTATE output immediately goes low and is held low for the time period specified by this constant ...
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... Name 0: fault issued from the power stage 1 FAULT 1: normal operation (no fault) Section 8.12, this register bit is set to '0' to indicate the error to the RST Name 0: normal operation (PLL locked state) 0 PLLUL 1: PLL unlock is detected (due to probable clock loss) STA323WQS Description Description Description ...
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... STA323WQS 9 Package information Figure 53. PowerSO-36 slug down mechanical data and package dimensions DIM. MIN 0. 0.22 c 0.23 D 15.80 D1 9.40 E 13.90 E1 10. 5. 15. 0 Note: “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions are " ...
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... The feature requiring license is: QXpander (QHD®) QHD and QXpander are intellectual property of QSounds Lab Inc. A license can be obtained with the STA323WQS via STMicroelectronics,please contact the HPC Audio Dividion Product Manager for details. Alternatively the license can be obtained directly from QSounds Lab Inc. ...
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... STA323WQS 11 Revision history Table 73. Document revision history Date 02-Jan-2007 Revision 1 Initial release Revision history Changes 71/72 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 72/72 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA323WQS ...