cp2120 Silicon Laboratories, cp2120 Datasheet
cp2120
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cp2120 Summary of contents
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... Supply Voltage of 2 3.6 V Typical operating current: 6.4 mA Package Pb-free 20-pin QFN Internal Oscillator Controller Port Controller Eight I/O Pins Edge-Triggered Figure 1. Block Diagram Copyright © 2007 by Silicon Laboratories SDA I C Interface SCL Interrupt Source CP2120 ...
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... CP2120 2 Rev. 0.3 ...
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... C Activity During SPI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1. Determining Pull-Up Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. Port I CP2120 Revision Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Rev. 0.3 CP2120 Page 3 ...
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... No external components other than 2 pull-up resisters on the I C pins are required. The SPI Master controls the CP2120 across the SPI interface using a command set that governs all CP2120 configuration and operation. 2. Absolute Maximum Ratings Table 1 ...
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... General Purpose Configurable Digital Input/Output General Purpose Configurable Digital Input/Output General Purpose Configurable Digital Input/Output General Purpose Configurable Digital Input/Output General Purpose Configurable Digital Input/Output General Purpose Configurable Digital Input/Output Edge-Triggered Interrupt Source CP2120 Interrupt Indicator Not connected, leave floating Rev. 0.3 CP2120 5 ...
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... CP2120 4.2. QFN-20 Pinout Diagram (Top View 2120 Rev. 0 ...
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... QFN-20 Pinout Diagram (Bottom View) Table 4.1. QFN-20 Package Dimensions Rev. 0.3 CP2120 MM MIN TYP MAX 0.80 0.90 1.00 0 0.02 0.05 0 0.65 1.00 — 0.25 — 0.18 0.23 0.30 — 4.00 — 2.00 2.15 2.25 — 4.00 — 2.00 2.15 2.25 — 0.5 — 0.45 0.55 0.65 — 20 — — 5 — — 5 — 0.09 — — — ...
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... CP2120 4.4. QFN-20 Solder Paste Recommendations 8 Rev. 0.3 ...
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... SPI with a clock source. Figure 2 shows typical connections for an SPI bus. SPI Master SPICLK SCLK should be held high when idle. Figure 3 shows a CP2120 data transfer on the SPI Bus. If the CP2120 is the only slave device on the SPI bus, the NSS pin can be tied low. SCK ...
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... CP2120 operation and events. 5.2. Internal Registers The CP2120 maintains a set of internal registers that can be modified to configure general purpose port I/O and I operation and can be read to obtain device status. Commands reading to and writing from the internal registers can be issued at any time, even while an I Table 3 shows a list of all internal registers ...
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... This byte is followed by the transmission of a "don't care" byte, which can be of any value and is ignored by the CP2120. After the "don't care" byte, the internal register value is transmitted across the MISO line. ...
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... Master device on the bus attempts to address the CP2120 during this time, the CP2120 will not ACK the address defined in the I2CADR Internal Register. If the SPI Master attempts to transmit a command to the CP2120 while the CP2120 is acting as the Master on the bus, the CP2120 will suspend I command ...
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... C Internal Registers 2 Features of the I C interface are configured through the CP2120's Internal Registers. SCL clock frequency is set by writing to the I2CCLK Internal Register. The frequency can be determined using the equation below. The I frequency configured by the I2CCLOCK register is only an approximate frequency. Actual I due to conditions on the bus, such as a slave device extending the SCL low time. ...
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... C address to the CP2120 by writing to the I2CADR Internal Register. Setting this address is not necessary for device operation. If set, the CP2120 will ACK this address when another I on the bus attempts to communicate with it. The CP2120 will NACK all attempts at data transfer when responding slave ...
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... C transaction completes (successfully or unsuccessfully), and when a received SPI command contains errors not recommended that an SPI master poll the CP2120's I2CSTAT Internal Register to determine when an I transaction has completed. The SPI master should instead watch for the INT pin to drop low, and then read the ...
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... CP2120 Internal Register Definition 5. I2CSTAT I2ST7 I2ST6 I2ST5 Bit 7 Bit 6 Internal Register Address: 0x04 Reset Value: 0x00 Bit 7– Status Value 2 0xF0 I C transaction completed successfully. 0xF1 Slave address NACKed. 0xF2 Slave data NACKed. 2 0xF3 I C transaction in progress. 2 0xF8 I C transaction timed out due to timer configured in I2CTO ...
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... C transaction completes, the CP2120 pulls the INT pin low and sets I2CSTAT according to the results of the transaction. The CP2120 saves the number of bytes stored in the buffer in the internal register named RXBUFF. A Read Buffer command can be issued to retrieve the bytes from the buffer. ...
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... CP2120's buffer before issuing a Read Buffer command. If the SPI Master attempts to retrieve more bytes than the buffer contains, the CP2120 will signal the error in I2CSTAT SPI Master attempts to retrieve fewer bytes than are stored in the data buffer, all bytes left in the buffer will be deleted when the Read Buffer command terminates ...
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... Once the interrupt has been configured and enabled, the CP2120 will pull the INT pin low when the port pin's logic value switches to “1'” or “0”, depending on the interrupt configuration specified in the EIT bit. When an interrupt is triggered, EIF in the EDGEINT Internal Register is set ...
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... CP2120 Internal Register Definition 8. IOCONFIG2: Port I/O Configuration 2 R/W R/W PCIO7.1 PCIO7.0 PCIO6.1 Bit 7 Bit 6 Internal Register Address: 0x07 Reset Value: 0x00 Bit 7-6: PCIO7.1-PCIO7.0: Port Configuration for GPIO Pin 7 Bit 5-4: PCIO6.1-PCIO6.0: Port Configuration for GPIO Pin 6 Bit 3-2: PCIO5.1-PCIO5.0: Port Configuration for GPIO Pin 5 Bit 1-0: PCIO4 ...
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... EIT: Edge Triggered Interrupt Trigger 0: Interrupt triggered on negative-to-positive digital transition on the EI_INT port pin. 1: Interrupt triggered on positive-to-negative digital transition on the EI_INT port pin. Bit 4–Bit 0: Not used. R/W R/W R/W Rsvd Rsvd Rsvd Bit 4 Bit3 Bit 2 Rev. 0.3 CP2120 R/W R/W Rsvd Rsvd Bit 1 Bit 0 21 ...
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... CP2120 8. CP2120 Revision Number The CP2120 revision number can be retrieved by first sending the Revision Number command byte of 0x40 and then transmitting one “don’t care” transitional byte. The CP2120 then transmits the two-byte revision number, most significant byte first, in BCD format. For example, a transmitted byte sequence of “0x01 0x44” would indicate that the CP2120’ ...
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... Added Table 3. Internal Register Addresses. Updated all CP2120 command drawings. Added section 6.1 Determining Pull-Up Register Values. Changed appearance of all Internal Register Definition charts. Changed contents of Section 8. CP2120 Revision Number. Revision 0.2 to Revision 0.3 Removed references to power down mode. Corrected Equation 1, “I2C Clock Frequency,” on page 13. ...
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... CP2120 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Email: MCUinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein ...