aduc847bs8-3 Analog Devices, Inc., aduc847bs8-3 Datasheet - Page 21

• Manufacturer Part Number: aduc847bs8-3
• Description: Microconverter, 10-channel 24-bit Adc With Embedded 62kb Flash Mcu
• Manufacturer: Analog Devices, Inc.

TABLE V
SF
Word
Signal Chain Overview (CHOP Disabled, CHOP = 1)
With CHOP =1 chopping is disabled. With chopping disabled the
available output rates vary from 16.06 Hz to 1.365 kHz .The range
of applicable SF words is from 3 to 255. When switching between
channels with chop disabled, the channel throughput rate is
increased over the case where chop is enabled. The drawback with
chop disabled is that the drift performance is degraded and
calibration is required following a gain change or significant
temperature change. A block diagram of the ADC input channel
with chop disabled is shown in Figure 8. The signal chain includes
a multiplexor, buffer, PGA, sigma-delta modulator, and digital
filter. The modulator bit stream is applied to a Sinc
programming of the Sinc
register SF, the actual decimation factor is the register value times
8. The decimated output rate from the Sinc
conversion rate) will therefore be:
where
f
SF is the decimal equivalent of the word loaded to the filter
register, valid range is from 3 to 255,
f
The settling time to a step input is governed by the digital filter. A
synchronized step change will require a settling time of three times
the programmed update rate, a channel change can be treated as a
synchronized step change. This means that following a
synchronized step change, the ADC will require three outputs
before the result accurately reflects the new input voltage.
REV. PrA 05/03
ADC
MOD
255
13
69
is the ADC conversion rate,
is the modulator sampling rate of 32.768 kHz.
: Peak to Peak Resolution (bits) vs Input Range and Update Rate for the ADuC847 with chopping Enabled
Data Update
Rate (Hz)
105.03
t
19.79
SETTLE
5.35
f
ADC
3
decimation factor is restricted to an 8-bit
=
=
8
f
×
ADC
3
1
±20 mV
SF
13.5
12
14
=
×
3
f
×
MOD
t
Figure 6: ADC Circuit Diagram with Chopping Enabled
ADC
3
±40 mV
filter (and the ADC
13
14
15
3
filter. The
±80 mV
14
15
16
-21-
±160 mV
15
16
17
An unsynchronized step change will require four outputs to
accurately reflect the new analog input at its output.
The allowable range for SF is 3 to 255 with a default of 69 (45H).
The corresponding conversion rates, RMS and Pk-Pk noise
performances are shown in Table VI & Table VII. Note that the
conversion time increases by 0.244 ms for each increment in SF.
ADC
DISABLED
Tables VII and VIII show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for some
typical output update rates. The numbers are typical and generated
at a differential input voltage of 0V. The output update rate is
selected via the SF7–SF0 bits in the SF Filter Register. It is
important to note that the peak-to-peak resolution figures represent
the resolution for which there will be no code flicker within a six-
sigma limit. The output noise comes from two sources.The first is
the electrical noise in the semiconductor devices (device noise)
used in the implementation of the modulator. Secondly, when the
analog input is converted to the digital domain, quantization noise
is added. The device noise is at a low level and is independent of
frequency. The quantization noise starts at an even lower level but
rises rapidly with increasing frequency to become the dominant
noise source. The numbers in the tables are given for the bipolar
input ranges. For the unipolar ranges the rms noise numbers will be
the same as the bipolar range, but the peak-to-peak resolution is
now based on half the signal range which effectively means losing
1 bit of resolution. Typically, the performance of the ADC with
Chop disabled will show a 1LSB degradation over the performance
with Chop enabled.
Input Range
±320 mV
NOISE
15
17
18
PERFORMANCE
±640 mV
15.5
17.5
18.5
±1.28 V
16
18
19
WITH
.
±2.56 V
18.5
19.5
16
CHOPPING