lm25066apsqx National Semiconductor Corporation, lm25066apsqx Datasheet - Page 15

• Manufacturer Part Number: lm25066apsqx
• Description: Lm25066a System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

Gate Control
A charge pump provides the voltage at the GATE pin to en-
hance the N-Channel MOSFET’s gate. During normal oper-
ating conditions (t
by an internal 22 µA current source. The voltage at the GATE
pin (with respect to ground) is limited by an internal 18.8 V
zener diode. See the graph “GATE Pin Voltage”. Since the
gate-to-source voltage applied to Q
V during various conditions, a zener diode with the appropri-
ate voltage rating must be added between the GATE and OUT
pins if the maximum V
less than 18.8 V. The external zener diode must have a for-
ward current rating of at least 190 mA. When the system
voltage is initially applied, the GATE pin is held low by a 190
mA pull-down current. This helps prevent an inadvertent turn-
on of the MOSFET through its drain-gate capacitance as the
applied system voltage increases.
During the insertion time (t
low by a 2 mA pull-down current. This maintains Q
state until the end of t
UVLO. Following the insertion time, during t
gate voltage of Q
dissipation level from exceeding the programmed levels.
While in the current or power limiting mode, the TIMER pin
capacitor is charging. If the current and power limiting cease
1
3
is modulated to keep the current or power
in
Figure
1
GS
, regardless of the voltage at VIN or
rating of the selected MOSFET is
1
in
2) the gate of Q
Figure
1
could be as high as 18.8
FIGURE 2. Power Up Sequence (Current Limit Only)
2) the GATE pin is held
1
2
is held charged
in
Figure 2
1
in the off-
the
15
before the TIMER pin reaches 1.7V the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If
the in-rush limiting condition persists such that the TIMER pin
reached 1.7V during t
190 mA pull-down current. The GATE pin is then held low until
either a power up sequence is initiated (RETRY pin to VDD),
or an automatic retry is attempted (RETRY pin to GROUND).
See the Fault Timer & Restart section. If the system input
voltage falls below the UVLO threshold, or rises above the
OVLO threshold, the GATE pin is pulled low by the 2 mA pull-
down current to switch off Q
Current Limit
The current limit threshold is reached when the voltage across
the sense resistor R
voltage limit of 25 mV or 46 mV depending on whether the CL
pin is connected to GND or VDD, respectively. In the current
limiting condition, the GATE voltage is controlled to limit the
current in MOSFET Q
the fault timer is active as described in the Fault Timer &
Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the
LM25066A resumes normal operation. If the current limit con-
dition persists for longer than the Fault Timeout Period set by
the timer capacitor, C
S
2
1
, the GATE pin is then pulled low by the
. While the current limit circuit is active,
(VIN to SENSE) exceeds the internal
T
, the IIN/PIN_FAULT bit in the
1
.
30146013
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