lm25066apsqx National Semiconductor Corporation, lm25066apsqx Datasheet - Page 17

• Manufacturer Part Number: lm25066apsqx
• Description: Lm25066a System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lock-out (OVLO) levels. Typically the UVLO level at
V
5. Refering to the Block Diagram when V
LO level, the internal 23 µA current source at UVLO is en-
abled, the current source at OVLO is off, and Q
the 2 mA pull-down current at the GATE pin. As V
creased, raising the voltage at UVLO above its threshold the
23 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With
the UVLO/EN pin above its threshold, Q
the 22 µA current source at the GATE pin if the insertion time
delay has expired.
See the Applications Section for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The mini-
mum possible UVLO level at V
the UVLO/EN pin to VIN. In this case Q
insertion time when the voltage at VIN reaches the POR
threshold. After power up an UVLO condition will cause the
INPUT_UNDER_VOLTAGE_FAULT bit in the STATUS_IN-
PUT (7Ch), and DIAGNOSTIC_WORD (E1h) registers to be
toggled high and SMBA pin will be pulled low unless this fea-
ture is disabled using the ALERT_MASK (D8h) register.
Over-Voltage Lock-Out (OVLO)
The series pass MOSFET (Q
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lock-out (OVLO) levels. If V
voltage above its threshold Q
down current at the GATE pin, denying power to the load.
When the OVLO pin is above its threshold, the internal 23 µA
current source at OVLO is switched on, raising the voltage at
OVLO to provide threshold hysteresis. When V
below the OVLO level Q
will toggle the INPUT_OVER_VOLTAGE_FAULT bit high in
the STATUS_INPUT (7Ch) and DIAGNOSTIC_WORD (E1h)
registers and the SMBA pin will be pulled low unless this fea-
ture is disabled using the ALERT_MASK (D8h) register.
SYS
is set with a resistor divider (R1-R3) as shown in
SYS
SYS
) is within the operating range defined by
) is within the operating range defined by
1
is re-enabled. An OVLO condition
1
is switched off by the 2 mA pull-
1
1
SYS
) is enabled when the input
) is enabled when the input
can be set by connecting
SYS
1
raises the OVLO pin
SYS
1
is enabled after the
is switched on by
is below the UV-
SYS
1
is held off by
FIGURE 4. Restart Sequence
is reduced
SYS
Figure
is in-
17
See the Applications Section for a procedure to calculate the
threshold setting resistor values.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO/EN pin below its threshold with an open collector or
open drain device, as shown in
UVLO/EN pin the LM25066A switches on the load current
with in-rush current and power limiting.
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain
of an internal N-channel MOSFET capable of sustaining 17V
in the off-state, and transients up to 20V. An external pull-up
resistor is required at PGD to an appropriate voltage to indi-
cate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. PGD is switched high when the voltage at the
FB pin exceeds the PGD threshold voltage. Typically the out-
put voltage threshold is set with a resistor divider from output
to feedback, although the monitored voltage need not be the
output voltage. Any other voltage can be monitored as long
as the voltage at the FB pin does not exceed its maximum
rating. Referring to the Block Diagram, when the voltage at
the FB pin is below its threshold, the 24 µA current source at
FB is disabled. As the output voltage increases, taking FB
above its threshold, the current source is enabled, sourcing
current out of the pin, raising the voltage at FB to provide
FIGURE 5. Shutdown Control
Figure
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5. Upon releasing the
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30146017