lm25066apsqx National Semiconductor Corporation, lm25066apsqx Datasheet - Page 18

• Manufacturer Part Number: lm25066apsqx
• Description: Lm25066a System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

www.national.com
threshold hysteresis. The PGD output is forced low when ei-
ther the UVLO/EN pin is below its threshold or the OVLO pin
is above its threshold. The status of the PGD pin can be read
via the PMBus interface in either the STATUS_WORD (79h),
DIAGNOSTIC_WORD (E1h) registers.
VDD Sub-Regulator
The LM25066A contains an internal linear sub-regulator
which steps down the input voltage to generate a 4.5V rail
used for powering low voltage circuitry. When the input volt-
age is below 4.5V, VDD will track VIN. For input voltages 3.3V
and below, VDD should be tied directly to VIN to avoid the
dropout of the sub-regulator. The VDD sub-regulator should
be used as the pull-up supply for the CL, CB, RETRY, ADR2,
ADR1, ADR0 pins if they are to be tied high. It may also be
used as the pull-up supply for the PGD and the SMBus signals
(SDA, SCL, SMBA). The VDD sub-regulator is not designed
to drive high currents and should not be loaded with other
integrated circuits. The VDD pin is current limited to 45mA in
order to protect the LM25066A in the event of a short. The
sub-regulator requires a bypass capacitance having a value
of 1 µF or greater to be placed as close to the VDD pin as the
PCB layout allows.
Remote Temperature Sensing
The LM25066A is designed to measure temperature remotely
using an MMBT3904 NPN transistor. The base and collector
of the MMBT3904 should be connected to the DIODE pin and
can be placed in the area or near the device of interest. If the
temperature of the hot-swap pass MOSFET, Q
sured, the MMBT3904 should be placed as close to Q
layout allows. The temperature is measured by means of a
change in the diode voltage in response to a step in current
supplied by the DIODE pin. The DIODE pin sources a con-
stant 9.4 µA but pulses 250 µA once every millisecond in order
to measure the diode temperature. Care must be taken in the
PCB layout to keep the parasitic resistance between the
DIODE pin and the MMBT3904 low so as not to degrade the
measurement. Additionally, a small 100 pF bypass capacitor
should be placed in parallel with the MMBT3904 to reduce the
effects of noise. The temperature can be read using the
READ_TEMPERATURE_1 PMBus command (8Dh). The de-
fault limits of the LM25066A will cause SMBA pin to be pulled
low if the measured temperature exceeds 125°C and will dis-
able the hot-swap pass MOSFET if the temperature exceeds
150°C. These thresholds can be reprogrammed via the PM-
Bus interface using the OT_WARN_LIMIT (51h) and
1
, is to be mea-
1
as the
18
OT_FAULT_LIMIT (4Fh) commands. If the temperature mea-
surement and protection capability of the LM25066A is not
used the DIODE pin should be grounded.
Damaged MOSFET Detection
The LM25066A is able to detect whether the external MOS-
FET, Q
across the sense resistor exceeds 4mV while the GATE volt-
age is low or the internal logic indicates that the GATE should
be
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD
(E1h) registers will be toggled high and the SMBA pin will be
pulled low unless this feature is disabled using the
ALERT_MASK register (D8h). This method effectively deter-
mines whether Q
the drain and gate and/or drain and source of the external
MOSFET.
Enabling/Disabling and Resetting
The output can be disabled at any time during normal opera-
tion by either pulling the UVLO/EN pin to below its threshold
or the OVLO pin above its threshold, causing the GATE volt-
age to be forced low with a pull down strength of 2mA.
Toggling the UVLO/EN pin will also reset the LM25066A from
a latched-off state due to an over-current or over-power limit
condition which has caused the maximum allowed number of
retries to be exceeded. While the UVLO/EN or OVLO pins can
be used to disable the output they have no effect on the
volatile memory or address location of the LM25066A. User
stored values for address, device operation, and warning and
fault levels programmed via the SMBus are preserved while
the LM25066A is powered regardless of the state of the UV-
LO/EN and OVLO pins.
The SMBus address of the LM25066A is captured based on
the states of the ADR0, ADR1, and ADR2 pins (GND, NC,
VDD) during turn on and is latched into a volatile register once
VDD has exceeded its POR threshold of 2.6V. Reassigning
or postponing the address capture is accomplished by holding
the VREF pin to ground. Pulling the VREF pin low will also
reset the logic and erase the volatile memory of the
LM25066A. Once released, the VREF pin will charge up to its
final value and the address will be latched into a volatile reg-
ister once the voltage at the VREF exceeds 2.4V. The output
may also be enabled or disabled by writing 80h or 0h to the
OPERATION (03h) register. To re-enable after a fault, the
fault condition should be cleared and the OPERATION (03h)
register should be written to 0h and then 80h.
low,
1
, is damaged under certain conditions. If the voltage
the
1
EXT_MOSFET_SHORTED
is shorted due to damage present between
bit
in
the