pi2eqx5804nje Pericom Semiconductor Corporation, pi2eqx5804nje Datasheet
pi2eqx5804nje
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pi2eqx5804nje Summary of contents
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Features • 5.0Gbps PCI Express Gen-2 Serial Re-driver • Supporting 8 differential channels or 4 lanes of PCIe Interface 2 • Pin strapped and I C confi guration controls (3.3V Tolerant) • Adjustable receiver equalization • Adjustable transmitter ...
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Pin # Pin Name Data Signals C4 A0RX+, B4 A0RX- C7 A0TX+, B7 A0TX- B1 A1RX+, C1 A1RX- B10 A1TX+, C10 A1TX- G3 A2RX+, G2 A2RX- G8 A2TX+, G9 A2TX- K2 A3RX+, K3 A3RX- K9 A3TX+, K8 A3TX- A8 B0RX+, ...
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H5 DE_B F8 LB# G5 MODE C6 PD# D6 PRSNT2# C5 RES_A# J5 RES_B# E10 RX50_A F1 RX50_B E7 RXD_A F4 RXD_B E6, E8 S[0:1]_A F5, F3 S[0:1]_B A5 SCL A6 SDA E1, E2, E3 SEL[0:2]_A I 07-0260 5.0Gbps 4-Lane ...
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F10, F9, F7 SEL[0:2] SIG_A F2 SIG_B Power Pins GND B2, B3, B8, B9, C2, C3, C8, C9, H2, H3, H8, H9, J2, J3, J8, J9 A1, A4, A7, VDD A10, B6, D1, D4, D7, D10, G1, G4, ...
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Equalizer Confi guration The PI2EQX5804 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) re- sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high- frequency signal components. Because either ...
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Output Swing Control S1_[A:B] S0_[A: Emphasis settings are determined by the state of the DEx_y input pins and confi guration registers, as shown in the Output De-emplasis table below. De-Emphasis is selected ...
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Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set to low, then the Receiver Detect operation for that group of channel is disabled, and those channels go directly ...
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Loopback Operation Each lane of the 5804 provides a loopback mode for test purposes which is controlled by a strapping pin and I2C register bit. The LB# pin controls all lanes together. When this pin is high normal data mode ...
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I2C Operation The integrated I2C interface operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing mode, with support for offset byte-write and read. The data byte format is 8 bit bytes. The bytes must be ...
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Transferring Data Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most signifi cant bit (MSB) fi rst (see the I will never ...
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Register Description Byte 0 - Signal Detect (SIG) SIG_xy=0=low input signal, SIG_xy=1=valid input signal Bit 7 6 Name SIG_A0 SIG_B0 Type R R Power- State Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future ...
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BYTE 3 - Channel Input Disable (INDIS) INDIS_xy=0=enable input, INDIS_xy=1=disable input Bit 7 6 Name INDIS_A0 INDIS_B0 Type R/W R/W Power- State Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Channel ...
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BYTE 6 - Power Down Control (PWR) PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup Bit 7 6 Name PD_A0# PD_B0# Type R/W R/W Power-on PD# PD# State Note: R=Read only, W=Write only, R/W=Read and ...
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Output Emphasis Confi guration earlier in this document for setting information. All four A channels get the same confi guration settings. BYTE 9 - B-Channels Equalizer and Output Control (BEOC) SELx_B: Equalizer confi guration, Dx_B: Emphasis control, Sx_B: Output ...
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I C Data Transfer 1. Read sequence ACK PI2EQX5804 Master DEV SEL 2. Write sequence ACK PI2EQX5804 Master DEV SEL 3. Combined sequence ACK PI2EQX5804 2 I ...
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Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................... Supply Voltage to Ground Potential........ –0.5V to +2.5V DC SIG Voltage....................................... –0. Current Output ........................................ –25mA to +25mA Power Dissipation Continuous ...
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Equalizer Symbol Parameter J Residual jitter RS-T J Residual jitter RS-D J Random jitter RM Notes 1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see fi gure). 2. Total jitter does not include ...
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SDA and SCL I/O for I2C-bus (V DD Symbol Parameter V DC input logic high input logic low output logic low OL V Hysteresis of Schmitt trigger input hys Characteristics of the SDA and ...
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START SDA t SU;DAT LOW SCL t HD;STA t HD;DAT S 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with HD;STA t SU;STA HIGH Sr I2C Timing Channel Latency, 5.0 Gbps 19 PI2EQX5804 Equalization & ...
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Output Level Settings (1V left, and 0.5V right at 5.0 Gbps) 0.0 dB (Dx = 000) –6.5 dB (Dx = 101) Output De-emphasis Characteristics 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with Equalization & Emphasis –3.5 dB (Dx = 010) ...
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Eye Diagrams 5.0Gbps (input left, output right) Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right) Signal Source Connector AC Test Circuit Referenced in the Electrical Characteristic Table 07-0260 5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with FR4 A B SmA SmA Connector ...
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... Packaging Mechanical: 100-Ball LFBGA (NJ) Notes: 1. All dimemsions are in millimeters 2. Ref JEDEC: MO-192 Ordering Information Ordering Number PI2EQX5804NJE Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • Pb-free and Green • X suffi Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0260 5 ...