pi2eqxdp101 Pericom Semiconductor Corporation, pi2eqxdp101 Datasheet

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pi2eqxdp101

Manufacturer Part Number
pi2eqxdp101
Description
1 To 1 Displayport? Redriver?
Manufacturer
Pericom Semiconductor Corporation
Datasheet
Block Diagram
Features
• DisplayPort™ 1.1a operation at reduced bit rate (1.62Gbps)
• Jitter elimination circuits automatically adjust link via training
• Can support all 4 levels of output swing and 4 levels output
• AUX interception circuit only listens to the link training, but
• Low insertion loss acros the AUX signal path (0.35dB
• Output can support dual mode DP by providing DDC signals
• Automatic power down state when HPD signal is LOW or no
• Dual power supply (1.5V and 3.3V)
• 2KV HBM ESD protection
• 50 ohm output termination can be turned off when port is off
• Package (Pb-Free & Green available)
AUX_SRC+
AUX_SRC-
and high bit rate (2.7Gbps)
path
pre-emphasis, as specifi ed in the DisplayPort 1.1a spec.
does not affect link training
@1Mbps)
across the AUX_sink pins
signal is present on the input high speed pins.
HPD_Sink
CAD_Sink
IN [3:0]±
SCL
SDA
 Pre-Emphasis, and output swing
 Using Cable Detect pin from DP connector (pin 13),
 Port is turned off automatically when not needed
 36-pin TQFN (ZF)
09-0099
the switch can toggle between DP and TMDS mode.
Logics
AUX CH
interpreter
register
HPD SRC
CAD SRC
Equalizer
Pre-emphasis
DDC
Pass
through
AUX
Pass
through
Bias
DDC_SCL/AUX+
DDC_SDA/AUX-
OUT [3:0]±
1
Description
The PI2EQXDP101 is a one Input and one Output DisplayPort™
ReDriver™ that support a maximum data rate of 2.7 Gbps through
each channel, which results in a total of 10.8Gbps through put.
Output Level Swing and Output Pre-emphasis and number of
active lanes are controlled by decoding the AUX command during
link initialization. Also, utilizing the HPD signals from each
DisplayPort port, the PI2EQXDP101 can automatically enter
power down state. Or, if the graphics driver is off and has no
output signal, Pericom’s PI2EQXDP101 can automatically enter
power down, even if an active monitor is attached.
Pin Diagram (Top-side View)
VDD15
GND
IN0+
IN1+
IN2+
IN3+
IN0-
IN1-
IN2-
IN3-
10
1
2
3
4
5
6
7
8
9
11
36
1 to 1 DisplayPort™ ReDriver™
12
35
13
34
14
33
15
32
16
31
17
30
PI2EQXDP101
18
29
PS9007B
28
27
26
25
24
23
22
21
20
19
OUT0-
GND
VDD15
OUT0+
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
05/11/09

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pi2eqxdp101 Summary of contents

Page 1

... Pass through 09-0099 Description The PI2EQXDP101 is a one Input and one Output DisplayPort™ ReDriver™ that support a maximum data rate of 2.7 Gbps through each channel, which results in a total of 10.8Gbps through put. Output Level Swing and Output Pre-emphasis and number of active lanes are controlled by decoding the AUX command during link initialization ...

Page 2

... Lane 0 data output, differential pair Output Lane 1 data output, differential pair Output Lane 2 data output, differential pair Output Lane 3 data output, differential pair Power Power Supply, 1.5V ± 5% Power Power Supply, 3.3V ± PI2EQXDP101 DisplayPort™ ReDriver™ SCL clock 2 C SDA data PS9007B 05/11/09 ...

Page 3

... Bit5 = MAX_PRE-EMPHASIS_REACHED Lane setting for lane 1. The defi nition is the same as lane 0 Lane setting for lane 2. The defi nition is the same as lane 0 Lane setting for lane 3. The defi nition is the same as lane 0 3 PI2EQXDP101 DisplayPort™ ReDriver™ Access R/W R/W R/W R/W R/W PS9007B ...

Page 4

... LANE_COUNT_SET 00103h TRAINING_LANE0_SET 00104h TRAINING_LANE1_SET 00105h TRAINING_LANE2_SET 00106h TRAINING_LANE3_SET Application Diagram DisplayPort Transmitter 09-0099 PI2EQXDP101 HPDSRC MAIN LINK IN± C AUX DDC CAD 4 PI2EQXDP101 DisplayPort™ ReDriver™ onto AUX CH Syntax is not supported. ReDRIVER HPD OUT± C DDC/AUX CAD_SINK PS9007B 05/11/09 ...

Page 5

... IOH=-8mA IOL= 8mA Condition Condition 5 PI2EQXDP101 DisplayPort™ ReDriver™ Note: Stresses greater than those listed under MAX I MUM RAT- INGS may cause permanent damage to the de vice. This is a stress rating only and func tion tion of the device at these or any other conditions above those indicated in the operational sections of this spec i fi ...

Page 6

... Mancester II coding Each pulse is a ‘0’ in Manches- ter 10 II code. V AUX-DIFFp-p 0.32 = 2*|V – AUX+ AUX- with 100-Ohm termination 0 1.3 The AUX CH AC coupling capacitor placed on the Display- 75 Port Source 6 PI2EQXDP101 DisplayPort™ ReDriver™ Nom Max Units 0.5 0.6 μ 1.36 V 1.5 2.0 dB 2 200 ...

Page 7

... RX lanes of a DisplayPort link. For High Bit Rate Maximum skew limit between D+ and D- of the same lane. For Reduced Bit Rate Maximum skew limit between D+ and D- of the same lane. 7 PI2EQXDP101 DisplayPort™ ReDriver™ Min. Typ. Max. Units 370 ps 617 ...

Page 8

... Time-domain measurement us- ing a spectrum analyzer. Total drive current of the trans- mitter when it is shorted to its ground. Straight loss line between 0.675 12 GHz and 1.35 GHz Straight loss line between 0.675 9 GHz and 1.35 GHz 8 PI2EQXDP101 Typ. Max. Units 370 ps 617 ps 1380 mV 400 460 ...

Page 9

... Informative. D+ rise to D- fall mismatch and D+ fall to D- rise mismatch. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the 75 transmitter side. Placement of AC coupling capacitors the receiver side is optional. 9 PI2EQXDP101 Typ. Max. Units 200 nF ...

Page 10

... Output Eye Diagram (2.7Gbps, 400mV) 09-0099 V DIFF DIFFp BIT Defi nition of Pre-emphasis Output Waveform (400mV, 6dB pre-emphasis) Output Eye Diagram (2.7Gbps, 1200mV) 10 PI2EQXDP101 DisplayPort™ ReDriver™ . Pre-emphasis = 20 Log DIFF-PRE DIFF V V DIFF-PRE DIFF BIT(s) PS9007B 05/11/09 ...

Page 11

... ReDriver is a trademark of Pericom Semiconductor. DisplayPort is a trademark of VESA www.vesa.org. DESCRIPTION: 36-contact, Very Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZF (ZF36) DOCUMENT CONTROL #: PD-2023 Package Code ZF 36-Contact, Pb-Free & Green (TQFN) 11 PI2EQXDP101 DisplayPort™ ReDriver™ DATE: 03/10/09 REVISION: C Package Description PS9007B 05/11/09 ...

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