tc5299j ETC-unknow, tc5299j Datasheet
tc5299j
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tc5299j Summary of contents
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... TC5299J FAST ETHERNET PCMCIA LAN CONTROLLER 4FL No. 106 Hsin-Tai Wu Road, Sec. 1, Hsichih, Taipei Hsien, Taiwan R.O.C. TEL: 886-2-2696-1669 FAX: 886-2-2696-2220 http:\\www.tmi.com.tw -1- TC5299J Ver. 0.1 07/04/01 ...
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... Attribute Memory Map ......................................................................................................................11 5 Configuration Registers ............................................................................................................13 5.1 Configuration Register A ..................................................................................................................................13 5.2 Configuration Register B ..................................................................................................................................13 5.3 Configuration Register C ..................................................................................................................................14 5.4 Hardware Configuration....................................................................................................................................14 5.5 MII/PHY Control Register ................................................................................................................................15 5.6 TC5299J Core Registers Assignment................................................................................................................15 5.7 Register Descriptions ........................................................................................................................................18 5.7.1 Command Register (CR) 00H (Read/Write) ......................................................................................18 5.7.2 Data Configure register (DCR) 0EH(Write) ....................................................................................19 5.7.3 Transmit configuration Register (TCR) 0DH(Write) ........................................................................19 5.7.4 Transmit Status Register (TSR) 04H(Read).....................................................................................20 5 ...
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... Introduction 1.1 General Description The TC5299J is a 10/100 PCMCIA Ethernet controller, include a standard MII interface. It provides an 8/16-bit PCMCIA interface to host CPU and buffer memory into single chip to minimize the chip gate count. The TC5299J supports both half-duplex and full-duplex (both 10BT or 100BTX) operation environment. ...
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... Ver. 0.1 07/04/01 TC5299J VCC3D VCC5A VCC5R VCC5A VCC3IO MDC RXD3 RXD2 GND3IO RXD1 RXD0 X25M RXDV RXC RXER GND3IO TXC TXEN TXD0 TXD1 GND3IO TXD2 TXD3 GND3D COL CRS VCC3IO ...
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... IO16* is driven by TC5299J to support host 16 bits access cycle. O While the TC5299J is configured as a memory device, this pin servers as RDY/BSY* pin, If the TC5299J is ready to perform a transfer, this pin is set high. When TC5299J is operated at I/O mode, this pin is used as an interrupt pin. It indicates that the TC5299J needs host service ...
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... I In MII mode this pin functions as the carrier sense and is asserted by the PHY when the media is active. O MII management data clock is sourced by the TC5299J to the external PHY devices as a timing reference for the transfer of information on the MDIO signal. I/O MII management data input/output transfers control information and status between the external PHY and the TC5299J ...
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... I/O. For PCMCIA system use only. Default setting is leaving this pin open. I Power on setting: 0: separate address decode. Decode range from A0 to A5. 1: full address decode. Decode range from A0 to A9. Description No Connection No Connection. Reserved for future use for PHY is included in a single chip. -7- TC5299J Ver. 0.1 07/04/01 ...
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... The TC5299J Controller configures itself after a RST signal is applied. When a Power-On-Reset occurs the TC5299J controller latches up the values on the configuration pins and uses these to configure the internal registers and options. Internally these pins contain pull-up resistance. If pins are unconnected they have default logic. The configuration registers are loaded JMP0 & ...
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... EEPROM's address space. Configuration Register A, B and C are located in the address 0EH. To write this configuration into the EEPROM, the user can program register in TC5299J's address 02H of page 3. This operation will work regardless of the level on EECONFIG. ...
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... Base+1FH The registers within this area are 8 bits wide, but the data transfer port is 16 bits wide. By accessing the data transfer port (using I/O instructions) the user can transfer data to or from the TC5299J 's internal memory. 4.2 EEPROM/SRAM Memory Mapping The TC5299J Controller's internal memory map is as shown below. ...
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... The TC5299J Controller includes 4 words cache internally remote read the TC5299J Controller moves data from memory buffer to the cache buffer; the TC5299J moves data continuously until the cache buffer is full remote write the system can writes data into the cache buffer until the 4 words cache buffer is full. ...
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... Card Configuration and Status Registers (R/W): 3FAH (CCR1 Name Description Ireq Interrupt. This bit describes the interrupt signal of LAN or MODEM 1: LAN interrupt 0: Modem interrupt XX Reserved Address Range 300H-31FH 320H-33FH 340H-35FH 360H-37FH -12- TC5299J D1 D0 Ireq XX Ver. 0.1 07/04/01 ...
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... The bit is indicated the decode-number of SA[9:0]. 0: Only decode 5 address-lines, SA[5:0]. 1: Full decode 10 address-lines, SA[9:0]. FREAD R/W The TC5299J Controller supports 4 words Remote DMA read/write cache. When this bit is set high, Remote DMA cache control will be enabled. XX Reserved PS. EL: The bit only set on EEPROM loading. ...
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... PS. X: Can’t read, just set these bit in the EEPROM. 5.4 Hardware Configuration These functions are configured during a power on RESET. Symbol I/O Description JMP0 I/O Power on setting: 0: Enter I/O mode (Same as CCR0, bit 5) JMP1 I/O Power on setting: 1: Full address decode(A9-A0) 0: Separate address decode(A5-A0 RBHI1 RBHI0 -14- TC5299J RBLO1 RBLO0 Ver. 0.1 07/04/01 ...
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... FIRQ This chip interrupt signal IRQ will be asserted when this bit is set high. READ TC5299J can reload CFGA, CFGB and internal PROM, if this bit is set high. When reload state is completed, READ will be cleared to low. ATTRDIS Attribute and common memory access will be disable programmed to high. ...
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... Pins A0-A3 are used to address registers within each page. Page 0 register are those registers which are commonly accessed during TC5299J Controller operation while Page 1 registers are used primarily for initialization. The registers are partitioned to avoid having to perform two read/write cycles to access commonly used registers. ...
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... Remote Next Packet Pointer Reserved Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RD Command(CR) Reserved Programming Reg. MII Control Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved -17- TC5299J Ver. 0.1 07/04/01 ...
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... The software reset has executed only when indicated by the RST bit in the ISR being set STP powers up high. D1 STA Start: This bit is used to active the TC5299J core after either power up, or when the TC5299J core has been placed in a reset mode by software command. STA power up low. D2 TXP Transmit Packet: This bit must be set to initiate transmission of a packet ...
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... Symbol Description 5.7.2 Data Configure register (DCR) This Register is used to program the TC5299J for 8 or 16-bit memory interface, select byte ordering in 16-bit applications and establish FIFO thresholds. The DCR must be initialized prior to loading the Remote Byte count Registers FT1 Bit ...
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... Encoded Loopback Control: These encoded configuration bits set the type of loopback that performed. Note that loopback in mode 2 sets the LPBK pin high, this places the TC5299J in loopback mode and that D2 of the DCR must be set to zero for loopback operation. Mode0 ...
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... Reserved Note: D2 and D3 are ”OR'd” together and D3 are set the TC5299J will accept broadcast and multicast addresses as well as its own physical address. To establish full promiscuous mode, bits D2, D3 and D4 should be set. In addition the multicast hashing array must be set to all 1's in order to accept all multicast addresses ...
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... Reception of the packet will be aborted. D4 MPA Missed Packet: Set when packet intended for node cannot be accepted by TC5299J because of a lack of receive buffers of if the controller is in monitor mode and did not buffer the packet to memory. Increments Tally Counter (CNTR2). ...
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... Frame Alignment Error - FIFO Overrun - Missed Packet - Excessive Collisions - FIFO Underrun - Set when TC5299J enters reset state and is cleared when a start command is issued - Set when a Receive Buffer Ring overflows and is cleared when leaves overflow status. Writing to this bit has no effect and powers up high. 5 ...
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... NC2 NC1 NC0 DA5 DA6 DA7 .. --------|--- Source DA2 DA1 DA0 DA10 DA9 DA8 DA18 DA17 DA16 DA26 DA25 DA24 DA34 DA33 DA32 DA42 DA41 DA40 FB2 FB1 FB0 FB10 FB9 FB8 FB18 FB17 FB16 FB26 FB25 FB24 Ver. 0.1 07/04/01 TC5299J ...
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... A12 A11 Transmit byte count register0, 1 (TBCR0, TBCR1): These two registers indicate the length of the packet to be transmitted in bytes. The maximum number of transmit bytes allowed is 32k bytes. (4000H – 7FFFH) The TC5299J will not truncate transmissions longer than 1500 bytes ...
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... Page start, stop registers (PSTART, STOP): The Page Start and Page stop Registers program the starting and stopping page of the Receive Buffer Ring. Since the TC5299J uses fixed 256-byte buffers aligned on page boundaries only the upper eight bits of the start and stop address are specified. ...
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... The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown as below CRDA1 A15 A14 A13 CRDA0 A12 A11 A10 A12 A11 A10 -27- TC5299J Ver. 0.1 07/04/01 ...
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... Electrical Specification and Timing MII : RECEIVE TIMING An example transfer a packet from PHY to MAC RXC RXDV RXD[3:0] RXER TRANSMIT TIMINGS An example transfer a packet from MAC to PHY TXC TXEN TXD[3:0] CRS COL Receive Data Transm it Data -28- TC5299J Ver. 0.1 07/04/01 ...
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... (Read (Write ISA Slave Accesses Data Valid -29- TC5299J Ver. 0.1 07/04/01 ...
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... Transfers Min Max Min 100 300 140 150 -30- TC5299J Units Max Ver. 0.1 ...
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... BASE b1 5 METAL SECTION B-B Dimension in inch Min Nom Max ------ 0.063 ------ ------ 0.055 0.057 0.007 0.009 0.006 0.007 ------ 0.008 ------ 0.006 0.630 0.636 0.551 0.555 0.630 0.636 0.551 0.555 0.016 BSC 0.024 0.030 0.039 REF ------ ------ ------ 0.008 ------ ----- ------ ------ TYP 12 12 TYP TC5299J Ver. 0.1 07/04/01 ...
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... Notice This document contains information on product, which is in the development phase. TMI reserves the rights to change specifications, features, functions and availability of the product without notice. TMI devices are NOT designed, intended, authorized, or warranted to be suitable for use in Life-Supporting applications. -32- TC5299J Ver. 0.1 07/04/01 ...