w83628f Winbond Electronics Corp America, w83628f Datasheet
w83628f
Available stocks
Related parts for w83628f
w83628f Summary of contents
Page 1
... Table of Content- 1. GENERAL DESCRIPTION .............................................................................................................. 3 2. FEATURES...................................................................................................................................... 3 3. PACKAGE........................................................................................................................................ 3 4. BLOCK DIAGRAM OF W83628F .................................................................................................... 4 5. BLOCK DIAGRAM OF W83629D.................................................................................................... 5 6. PIN CONFIGURATION.................................................................................................................... 6 6.1 PIN CONFIGURATION FOR 628F........................................................................................ 6 6.2 PIN CONFIGURATION FOR 629D ....................................................................................... 7 7. PIN DESCRIPTION ......................................................................................................................... 8 7.1 W83628F PIN DESCRIPTION............................................................................................... 8 7.1.1 PCI Interface .......................................................................................................................... 8 7.1.2 Control Logic and Handshaking Signals ................................................................................. 9 7.1.3 ISA Interface Signals ............................................................................................................ 10 7 ...
Page 2
... WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1................................................ 21 8.28 WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2................................................ 22 8.29 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3................................................ 22 8.30 WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4................................................ 23 8.31 WISA_TSTREG-ISA BRIDGE TEST REGISTER................................................................ 23 9. PACKAGE DIMENSIONS 1 FOR W83628F (128-PIN PQFP) ..................................................... 24 10. PACKAGE DIMENSIONS 2 FOR W83629D (48-PIN LQFP) ....................................................... 24 11. REVISION HISTORY..................................................................................................................... 25 W83628F & W83629D -2- ...
Page 3
... For the new generation Intel chipset Camino and Whitney, featuring LPC bus, there is no support for ISA bus and slots. However the demand of ISA devices still exist. For such case, W83628F plus W83629D are the best companion solution for the non-ISA chipset. Also the packages of W83628F (128-QFP) and W83629D (48-LQFP) had been chosen to be the most economic solution for save the M/B board layout size and cost ...
Page 4
... BLOCK DIAGRAM OF W83628F AD[31:0] C/BE[3:0]# PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL SERR# NOGO PCIRST# PCICLK ISOLATE# 3.3V 5V PCI Interface Interface Signal Isolation Control Power SuppIy Handshaking -4- W83628F & W83629D SA[19:0] SD[15:0] BALE AEN IOCHRDY IOCS16# IOCHK# IOR# ISA IOW# LA[23:17] SBHE# MEMCS16# MEMR# MEMW# SMEMR# SMEMW# ...
Page 5
... BLOCK DIAGRAM OF W83629D PCIRST# PCICLK NOGO HS[2:0] ISAREQ# ISAGNT# SERIRQ 3.3V 5V PCI Host & Bridge Set Handshaking Logic PCI/PCI Interface Serial to Parallel IRQ Power SuppIy - 5 - W83628F & W83629D DREQ[7:5,3:0] DACK[7:5,3:0]# TC IRQ[15,14,12:9,7:3] Publication Release Date: May 18, 2005 Revision A1 ...
Page 6
... -6- W83628F & W83629D ...
Page 7
... W83628F & W83629D DACK2# 24 DRQ1 DACK1# DRQ0 DACK0# TC GND HS2 HS1 HS0 VCC IRQ15 Publication Release Date: May 18, 2005 Revision A1 ...
Page 8
... CMOS level Schmitt-trigger input pin TTL level input pin TTL level input pin with internal pull down resistor TTL level Schmitt-trigger input pin IN tsp3 - 3.3V TTL level Schmitt-trigger input pin 7.1 W83628F PIN DESCRIPTION 7.1.1 PCI Interface SYMBOL PIN I/O 19-26 30-37 I/O 24tp3 AD[31:0] 52-59 ...
Page 9
... System Error. SERR# can be pulsed active by any PCI agent that detects a system error condition. Parity Signal. W83628F generates even parity across AD[31:0] and C/BE[3:0]#. PCI Reset. W83628F receives PCIRST reset from the PCI Bus. FUNCTION Handshaking Signals. HS[2:0] connected to W83629D for PCI to ISA SET handshaking signals. ...
Page 10
... ISA System Clock. SYSCLK is the reference clock for the ISA bus. The SYSCLK is generated by dividing PCICLK Reset Drive. W83628F asserts RSTDRV to reset devices that reside on the ISA Bus. The W83628F asserts this signal while the PCIRST# is asserted. 16-bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles ...
Page 11
... ISA bus cycle is a memory write cycle to an address below 1 Mbyte. Bus Address Latch Enable. BALE is an active high signal asserted by the W83628F to indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE ...
Page 12
... PCI bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. PCI Reset. W83628F receives PCIRST reset from the PCI Bus. FUNCTION ISA Bus Request. This signal is a point-to-point signal between W83629D and a PCI HOST arbiter ...
Page 13
... NC 36, 37,38, 39, 45 I/O Serial Interrupt Requested Signals. This signal is for transfer IRQ mode between parallel IRQ to serial IRQ Parallel Interrupt Requested Input. I/O PWR 5V Supply. PWR 3.3V Supply. PWR Ground. I/O No Connection W83628F & W83629D FUNCTION FUNCTION FUNCTION Publication Release Date: May 18, 2005 Revision A1 ...
Page 14
... Fast Back to Back. This bit always returns a zero. Bit 8 SERR# Enable. =1 Enable. =0 Disable. Bit 7 Wait Cycle Control(Not supported). Hardwired to zero. Bit 6 Parity Error Response(Not supported). Hardwired to zero. Bit 5 VGA Palette Snoop Enable(Not supported). Hardwired to zero. Bit 4 Memory Write and Invalidate Enable(Not supported). Hardwired to zero. W83628F & W83629D -14- ...
Page 15
... This bit is set when the ISA bridge signals a target abort for a PCI transaction. Software sets this bit writing it. Bit 10:9 DEVSEL# Timing. This 2 bits always return a 01b(medium decode). Bit 8 Data Parity Detected(Not supported). Hardwired to zero. Bit 7 Fast Back-to-Back(Not supported). Hardwired to zero. W83628F & W83629D Publication Release Date: May 18, 2005 - 15 - Revision A1 ...
Page 16
... The register is a read-only register and used to indicate that the ISA bridge configuration space adheres to PCI local bus specification. It also indicates that ISA bridge is not a multifunction device. Bit 7 Multifunction Indicator Not a multifunction device. Bit 6:0 Layout Code. 00h = PCI layout type. W83628F & W83629D -16- ...
Page 17
... The 16-bit I/O recovery time is decided by bits 1:0. Bit 1:0 16-bit I/O Recovery Times. When bit 2=1 ,this 2-bit field defines the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 16 bit I SYSCLK = 10 2 SYSCLKs = 11 3 SYSCLKs = 00 4 SYSCLKs W83628F & W83629D Publication Release Date: May 18, 2005 - 17 - Revision A1 ...
Page 18
... WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL REGISTER Address Offset: 59h Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 1, if the corresponding bit of this register is set the corresponding address bit(A7~A0) is ignore by the faster address decoder # 1. W83628F & W83629D -18- ...
Page 19
... Default Value: 00h Attribute: Read/Write This register is used to mask address bits(A7~A0) for fast address decoder # 6, if the corresponding bit of this register is set the corresponding address bit(A7~A0) is ignore by the faster address decoder # 6. W83628F & W83629D Publication Release Date: May 18, 2005 - 19 - Revision A1 ...
Page 20
... Attribute: Read/Write This register contains the base address for fast address decoder # 3. 8.23 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS REGISTER Address Offset: 68-69h Default Value: 0000h Attribute: Read/Write This register contains the base address for fast address decoder # 4. W83628F & W83629D -20- ...
Page 21
... Enable High-Address BIOS ROM decoder. This bit can be set/reset by ROMCS# power-on setting during PCIRST# assert. Bit 0 =0 Normal mode. =1 Disable ISA Bridge subtraction decoder. This bit can be set/reset by HS1 power-on setting during PCIRST# assert. W83628F & W83629D Publication Release Date: May 18, 2005 - 21 - Revision A1 ...
Page 22
... Bit 0 =0 Enable IRQ3. =1 Disable IRQ3. 8.29 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3 Address Offset: 72h Default Value: 00h Attribute: Read/Write Bit 7-3 Reserved. Bit 2 =0 Enable IRQ15. =1 Disable IRQ15. Bit 1 =0 Enable IRQ14. =1 Disable IRQ14. Bit 0 =0 Enable IRQ12. =1 Disable IRQ12. W83628F & W83629D -22- ...
Page 23
... PIIX4 for test set the bit Bit 3 Reserved and should not write data to this register. Bit 2-0 000 - 0.8 nS. 001 - 0.6 nS. 010 - 0.4 nS. 011 - 0.2 nS. 100 0 nS. 101 +0.2 nS. 110 +0.4 nS. 111 +0.6 nS. W83628F & W83629D For Winbond Internal Reference only. Publication Release Date: May 18, 2005 - 23 - Revision A1 ...
Page 24
... PACKAGE DIMENSIONS 1 FOR W83628F (128-PIN PQFP 102 65 103 128 See Detail F y Seating Plane 10. PACKAGE DIMENSIONS 2 FOR W83629D (48-PIN LQFP See Detail F Seating Plane Detail F 24 ...
Page 25
... Supports 3 fully ISA Compatible Slots without Buffering. Rename HS3 renamed to ROMCS# in W83628F,and NC in W83629D. Indicate the Bit 4 of offset address 80h is used to enable 80h port decoding when only positive decoding switched of LPC I/F. 25 ADD Important Notice ...