l4969 STMicroelectronics, l4969 Datasheet - Page 15

• Manufacturer Part Number: l4969
• Description: System Voltage Regulator With Fault Tolerant Low Speed Can-transceiver
• Manufacturer: STMicroelectronics

1.9
The device features three independent thermal warning circuits which monitor the temperature of the V1 output,
the V2 output and the CAN_H and CAN_L drivers together with voltage regulator V3. Each circuit sets a sepa-
rate overtemperature flag in a register which is read and writable by the serial interface. The overtemperature
flags cause an interrupt to the C. The C is able to switch V1, V2 and CAN drivers on and off through dedicated
enable registers. To enhance system security following strategy is chosen for thermal warning and shutdown:
– 3 independent warning flags are set at 140°C for V1, V2 and V3 /CAN-Transceiver
– at 170°C V2 and V3 switched off
– at 200°C V1 is switched off
– V2 and V3 can be switched on again through the C
– V1 can be switched on again at wake-up (Watchdog wake-up, CAN wake-up, external wake-up)
Note, that if no wakeup source is set for V1 a 1sec watchdog timeout will be established to enable a proper retry
cycle.
1.10 Serial Interface (SPI)
A standard serial peripheral interface (SPI) is implemented to allow access to the internal registers of the L4969.
A total of 12 Registers with different datalengths can be directly read from or written to, providing the requested
address at the beginning of a dataframe. Upon every access to this interface, the content of the register currently
accessed is shifted out via SOUT. All operations are performed on the rising edge of SCLK.
If a frame is not completed, the interface is automatically reset after 1.5ms of SCLK idle time (auto timeout de-
tection). If a message is corrupted (additional or missing SCLK pulses), the application software can detect this
by evaluating the returned value of the crc and force a communication gap of min 1.5ms to allow communicva-
tion recovery. A corruption can be caused during startup of the uC and SPI initialization. The application should
then wait at least 1.5ms after SPI init prior to starting the communication.
The dataframe format used described on the next page:
1.10.1General Dataframe Format:
Data is sampled on the rising edge of the clock and SOUT will change upon SCLK falling. SOUT will show a
copy of SIN for the Address/Command field for initial data path checks. Independent of the command state,
SOUT will show the content of the register addressed. SIN contains either data to be written or arbitrary data
for all other operations. The transaction will be terminated with four bit of data followed by a 4-Bit wide CRC
(Cyclic Redundancy Check) as a result of either SIN related data or calculated automatically on data returned
via SOUT. Here the C has to provide the correct sequence in order to get the write command activated inside.
A CRC-failure is signalled via NINT. For returned data the CRC can also be used to verify a successful transfer.
99AT0015
SIN
SOUT
SCLK
Thermal Protection
7
7
ADR/CMD
ADR/CMD
0
0
15
15
Datafield 1 (W/R)
Datafield 1 (R)
8
8
23
23
Datafield 2/CRC (W/R)
Datafield 2/CRC (R)
15
15
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