pef22554e Infineon Technologies Corporation, pef22554e Datasheet
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QuadFALC Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEF 22554 HT Version 2.1 PEF 22554 E Version 2.1 Preface This document describes the changes implemented in the QuadFALC related to the previous version ...
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Overview 1.1 Functional Changes The following function has been changed: • Version status in register VSTR changed from 02 • The boundary scan part number changed to 142, the boundary scan ID changed new BSDL file ...
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In order to minimize power consumption also possible to operate the device using separate external 3.3 V and 1.8 V supplies. Please note that the 1.8 V supply requires ...
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Pinout 108 104 XL1_1/XDOP1/XOID1 109 VDDX XL2_1/XDON1/XFM1 TDI 112 TDO VDDR RL1_1/RDIP1/ROID1 RL2_1/RDIN1/RCLKI1 116 VSSR VDDC RCLK1 XPA1 120 XPB1 XPC1 XPD1 VDDP 124 VSS XPA2 XPB2 XPC2 128 XPD2 RCLK2 TRS VDDP 132 MCLK VSEL VSSP VSSR 136 ...
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XL1_2 XL2_2 VDDR VSSR RL1_2 RL2_2 RL2_1 RL1_1 VSSR VDDR XL2_1 XL1_1 A VSSX VSSX XDI1 MCLK B SCLKX VDDX VDDX TCK C 1 RPC1 RPA1 RPB1 RPD1 D SCLKR RDO1 VDD VDD E 1 SCLKR ...
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A XL1_1 XL2_1 VDDR B VSSX VSSX D15 XPB1 C VDDX VDDX D14 TDO D D11 D13 D12 TDI E D10 VDD VDD VSS VDD ...
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Pin Description Table 1 Additional Pin Functions VSEL Voltage Select Enables the internal voltage regulator for 3.3 V-only operation mode if connected to V Disables the internal voltage regulator for dual power supply mode if connected ...
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Table 2 BGA Pin Assignment (cont’d) Ball No. Pin No. Symbol BGA TQFP K12 82 A8 K11 83 A9 B12 107 D15 C12 106 D14 D13 105 D13 D12 104 D12 D14 103 D11 E14 100 D10 F11 99 D9 ...
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Table 2 BGA Pin Assignment (cont’d) Ball No. Pin No. Symbol BGA TQFP A6 138 RL1 RL1 RL1.4 A8 116 RL2.1 A7 137 RL2 RL2 RL2.4 A13 109 XL1.1 A2 144 XL1.2 ...
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Table 2 BGA Pin Assignment (cont’d) Ball No. Pin No. Symbol BGA TQFP F3 13 SCLKR2 J4 26 SCLKR3 L1 31 SCLKR4 D2 4 RPA1 F4 14 RPA2 H4 22 RPA3 L3 32 RPA4 D3 5 RPB1 G2 15 RPB2 ...
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Table 2 BGA Pin Assignment (cont’d) Ball No. Pin No. Symbol BGA TQFP L6 51 XPA3 N8 57 XPA4 B11 121 XPB1 C8 127 XPB2 N7 52 XPB3 L8 58 XPB4 C9 122 XPC1 B5 128 XPC2 N5 53 XPC3 ...
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Table 2 BGA Pin Assignment (cont’d) Ball No. Pin No. Symbol BGA TQFP C13, C14 110 VDDX C1, C2 143 VDDX M1 VDDX M13, 71 VDDX M14 B13, B14 108 VSSX B1 VSSX N1 ...
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Decoupling Capacitors To gain best performance, the following values are recommended for the external decoupling capacitors between V required on each V pin. DDC Table 3 Decoupling Capacitor Parameters Parameter Capacitance Capacitor material ESR Loop inductance ( ...
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Operation Description E1/T1/J1 Note: Write access to unused register addresses: should be avoided, or set to “00” hex in address range xA9; must be avoided in address range above xA9 if not defined elsewhere (for example in ...
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Device Marking Pattern The sales code changed from PEB 22554 Version 1.3 to PEF 22554 Version 2.1. The new marking pattern is: Engineering Samples PTQFP: PEF 22554 HT V2.1 QuadFALC ES A21 Engineering Samples PBGA: PEF 22554 E V2.1 ...
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Flexible Clock Mode Settings The register settings for flexible master clock can be calculated as follows. For some standard frequencies see Table 5 located in registers GCM1 to GCM8. 1. PLL_M and PLL_N must fulfill the equations: a. for ...
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PHSN_E1, PHSN_T1 15; 3. Calculation of correction value for frequency mismatch correction: æ è PHD_E1 = 12288 × PHSN_E1 æ è PHD_T1 = 12288 × PHSN_T1 The result of these equations will be in the range of -2048...+2047. ...
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Register Modifications Framer Mode Register 2 (Read/Write) Value after reset FMR2 AFRS MCSP AFRS Automatic Force Resynchronization Search for next candidate automatically, if multiple candidates are present and the current candidate is incorrect. (This bit is ...
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Line Interface Mode 0 (Read/Write) Value after reset LIM0 XFB XDOS EQON By setting EQON = 1 the QuadFALC long haul mode automatically. After changing the value of EQON a receiver reset (CMDR.RRES) is required. For E1 ...
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Common Configuration Register 5 (Read/Write) Value after reset CCR5 CSF2 1) T1 mode only CSF2 Compare Status Field - Mode 2 If the status fields of consecutive LSSUs are equal, only the first is stored and every ...
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Global Clock Mode Register 5 (Read/Write) Value after reset GCM5 0 0 GCM5.7 removed bit set to 0 Global Clock Mode Register 6 (Read/Write) Value after reset GCM6 0 0 PLLN_5 PLLN_4 ...
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Global Clock Mode Register 8 (Read/Write) Value after reset GCM8 1 PHSX_ PHSX_ T12 GCM8.7 added bit set to 1 PHSX_T1(2:0) added bits PHSN_T1(3:0) added bits Channel Interrupt Status Register (Read) 7 CIS PLLL 0 ...
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Table 6 Pulse Shaper Programming (T1/J1) Range in Range in XPM0 m ft 122 266 to 399 D9 122 to 162 399 to 533 FC 162 to 200 533 to 655 3F 1) Register values of V1.3 may ...
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Electrical Characteristics Due to the change of silicon technology some of the electrical characteristics have changed. 2.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature IC supply voltage (pads, digital) IC supply voltage (core, digital) IC supply ...
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Operating Range Parameter Ambient temperature Supply voltages Analog input voltages Digital input voltages Ground 1) Voltage ripple less than these 3.3V supplies 2) Depending on the applied power supply level, signal clipping may occur due to ...
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Changed DC Characteristics Parameter Input high voltage Average power supply current (analog line interface mode) Average power supply current (digital line interface mode) Transmitter leakage current Receiver sensitivity E1 long haul Loss of signal (LOS) 4)5) detection limit 1) ...
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Changed Supply Power Test Conditions T1/J1 Parameter Pulse Mask Programming Delta Sheet Electrical Characteristics Symbol Test Unit Notes Values XPM2 01 H XPM1 16 H XPM0 95 H 27/30 ® QuadFALC PEF 22554 2002-09-16 ...
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Package Outlines P-BGA-160-1 (Plastic Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Delta Sheet Electrical Characteristics 28/30 ® QuadFALC ...
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Appendix The calculation of the GCM register values is supported by a PC-based tool which is available for free. A screenshot is shown in Figure 8 Flexible Master Clock Calculator Delta Sheet Figure 8 below. 29/30 ® QuadFALC PEF ...
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Figure 9 Application Wizard Delta Sheet 30/30 ® QuadFALC PEF 22554 Appendix F0234 2002-09-16 ...