pef20324 Infineon Technologies Corporation, pef20324 Datasheet

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pef20324

Manufacturer Part Number
pef20324
Description
Multichannel Network Interface Controller With 128 Channels Extended
Manufacturer
Infineon Technologies Corporation
Datasheet

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ICs for Communications
Multichannel Network Interface Controller for HDLC + Extensions
MUNICH128X
PEB 20324 Version 2.2
Hardware Reference Manual 04.99
DS 1

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pef20324 Summary of contents

Page 1

ICs for Communications Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X PEB 20324 Version 2.2 Hardware Reference Manual 04. ...

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PEB 20324, PEF 20324 Revision History: Current Version: 04.99 Previous Version: Product Overview 12/97 DS3 Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Chapter 6 Chapter 5 Updated. Tables 1...8 Tables 2-1 Pin ...

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Preface The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160- pin MQFP package, making ...

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Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 1-1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 2-1 Pin Descriptions by Functional Block: Port 0 Serial Interface . . . . . . . 17 Table 2-2 Pin Descriptions by Functional Block: Port 1 Serial Interface . . . . . . . ...

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Introduction The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160- pin MQFP package, ...

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Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X Version 2.2 1.1 Features Four independent 24/32-channel HDLC PCM Controllers with common PCI interface. Each of them provides: • Dedicated 1024 byte Tx Buffer • Dedicated 1024 byte Rx Buffer • ...

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Bit Processor Functions (adjustable for each channel) – HDLC Protocol – Automatic flag detection – Shared opening and closing flag – Detection of interframe-time-fill change, generation of interframe-time-fill ‘1’s or flags – Zero bit insertion – Flag stuffing and ...

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Bit / 33 MHz PCI 2.1 Interface • 32 Bit / 33 MHz De-multiplexed Bus Interface Option • 0.5 m, 3.3 V-Optimized Technology • 3.3 V I/O Capability with 5.0 V Input Tolerance • 160-pin MQFP Package Hardware ...

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Logic Symbol • AD(31:0) C/BE(3:0) PAR FRAME IRDY TRDY STOP PCI IDSEL BUS DEVSEL PERR SERR REQ GNT CLK RST INTA (de-multiplexed address bus) Figure 1-2 Logic Symbol Hardware Reference Manual JTAG Test Interface MUNICH128X PEB 20324 PEF 20324 ...

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Typical Applications The MUNICH128X provides protocol processing and host memory buffer management for four independent T1/E1 PRI ports. As such, the MUNICH128X fits into a system between the framer or LIU/framer devices (e.g., the Siemens FALC transceiver) and the ...

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T1/E1/PRI R FALC FALC -LH Transceiver Figure 1-4 System Integration of the MUNICH128X in De-multiplexed System Hardware Reference Manual T1/E1/PRI T1/E1/PRI R R FALC 54 / FALC FALC -LH FALC -LH Transceiver Transceiver ...

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Differences to the MUNICH32 • 128-channel capability • Symmetrical Rx and Tx Buffer Descriptor formats for faster switching • Improved Tx idle channel polling process for significantly reducing bus occupancy of idle Tx channels • Dedicated 1024 byte Tx ...

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Pin Descriptions 2.1 Pin Diagram (top view) • 120 117 114 111 TDI 121 DPCI0 DPCI1 A27 124 A26 A25 V 127 DD3 V SS A24 A23 130 A22 A21 A20 133 V DD3 136 DD3 ...

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Pin descriptions in Tables 2-1 to 2-8 are grouped by functional block, as shown by the heading for that group. Pin types are indicated by abbreviations: Signal Type Definitions: The following signal type definitions are partly taken from the PCI ...

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Table 2-1 Pin Descriptions by Functional Block: Port 0 Serial Interface Pin No. Symbol Type Description 114 RxCLK0 I 112 RxD0 I 113 RSP0 I 108 TxCLK0 I 110 TxD0 O 109 TSP0 I 111 TxDEN0 O Hardware Reference Manual ...

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Table 2-2 Pin Descriptions by Functional Block: Port 1 Serial Interface Pin No. Symbol Type Description 107 RxCLK1 I 105 RxD1 I 106 RSP1 I 97 TxCLK1 I 99 TxD1 O 98 TSP1 I 100 TxDEN1 O Hardware Reference Manual ...

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Table 2-3 Pin Descriptions by Functional Block: Port 2 Serial Interface Pin No. Symbol Type Description 96 RxCLK2 I 94 RxD2 I 95 RSP2 I 90 TxCLK2 I 92 TxD2 O 91 TSP2 I 93 TxDEN2 O Hardware Reference Manual ...

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Table 2-4 Pin Descriptions by Functional Block: Port 3 Serial Interface Pin No. Symbol Type Description 89 RxCLK3 I 85 RxD3 I 86 RSP3 I 81 TxCLK3 I 83 TxD3 O 82 TSP3 I 84 TxDEN3 O Hardware Reference Manual ...

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Table 2-5 Pin Descriptions by Functional Block: PCI Interface Pin No. Symbol Type Description 2, 5…8, AD(31:0) t/s 11…13, 30, 33…36, 39…41, 45…48, 51…54, 148, 149, 152…156, 159 14, 29, 42, C/BE(3:0) t/s 160 28 PAR t/s Hardware Reference Manual ...

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Table 2-5 Pin Descriptions by Functional Block: PCI Interface (cont’d) Pin No. Symbol Type Description 19 FRAME s/t/s 20 IRDY s/t/s 21 TRDY s/t/s 23 STOP s/t/s Hardware Reference Manual Frame FRAME indicates the beginning and end of an access. ...

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Table 2-5 Pin Descriptions by Functional Block: PCI Interface (cont’d) Pin No. Symbol Type Description 1 IDSEL I 22 DEVSEL s/t/s 26 PERR s/t/s 27 SERR o/d 147 REQ t/s Hardware Reference Manual Initialization Device Select When MUNICH128X is slave ...

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Table 2-5 Pin Descriptions by Functional Block: PCI Interface (cont’d) Pin No. Symbol Type Description 146 GNT t/s 145 CLK I 142 RST I 57 INTA O (o/ d) Hardware Reference Manual Grant This signal is asserted by the arbiter ...

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Table 2-6 Pin Descriptions by Functional Block: DEMUX Interface (additional signals to PCI Interface) Pin No. Symbol Type Description 122, 123 DPCI(1:0) I 58…61, A(27:2) I/O 66…70, 73…76, 79, 124…126, 129…133, 138…141 80 W/R I/O Hardware Reference Manual PCI/De-multiplexed Mode ...

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Table 2-7 Pin Descriptions by Functional Block: Power Supply Pin No. Symbol Type Description 4, 10, 18 25, 32, 38, 44, 50, 56, 63, 65, 72, 78, 88, 101, 104, 118, 128, 135, 137, 144, 151, 158 ...

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Table 2-8 Pin Descriptions by Functional Block: Test Interface Pin No. Symbol Type Description 115 TCK I 116 TMS I 121 TDI I 120 TDO O 119 TRST I Hardware Reference Manual JTAG Test Clock A Pull-Up resistor to V ...

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Functional Description 3.1 Functional Overview The MUNICH128X provides four independent “cores” as well as global functional blocks (see Figure 3-1). 3.2 Block Diagram • PCM - BUS Serial PCM/IF 24/32 Channel 64 Channel Figure 3-1 Block Diagram Hardware Reference ...

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Functional Blocks Each core consists of dedicated circuitry: Serial PCM Interface Controller, Configuration and State RAM (CSR), 24/32-channel HDLC Controller with internal Transmit and Receive Buffers, 64-Channel DMA Controller, and Register Set. 3.3.1 Serial PCM Interface Controller This block ...

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Tx Block Transmit Buffer (TB) The Tx Block of the HDLC Controller contains a 1024 byte buffer (TB) which may be allocated to all 32 channels of one cove equally (i.e., 2-DWords per channel) or may be allocated based ...

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Rx Block Receive Buffer (RB) The Rx Block of the HDLC Controller contains a 1024 byte buffer (RB) which is allocated to channels via requests from the protocol controller, as determined by the received data for each channel. HDLC ...

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DMA Controller Block This block controls memory address calculation, buffer management (including linked- lists) and interrupt processing. The 24/32-channel HDLC Controller has a dedicated DMA channel for each channel and direction. During run-time, the DMA Controller performs operations ...

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Global Functional Blocks The MUNICH128X provides global functional blocks for the Internal Bus, Arbiter, and 32 Bit / 33 MHz PCI 2.1 Interface as well as De-multiplexed Bus Interface Controller. 3.4.1 Internal Bus This block of the MUNICH128X interfaces ...

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System Integration The MUNICH128X provides protocol processing and host memory buffer management for four independent T1/E1 PRI ports. As such, the MUNICH128X fits into a system between the framer or LIU/framer devices (e.g., the Siemens FALC transceiver) and the ...

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T1/E1/PRI R FALC FALC -LH Transceiver Figure 3-2 System Integration of the MUNICH128X in De-multiplexed System Hardware Reference Manual T1/E1/PRI T1/E1/PRI R R FALC 54 / FALC FALC -LH FALC -LH Transceiver Transceiver ...

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Operational Description 4.1 Operational Overview The MUNICH128X is a “channelized” WAN protocol controller that performs protocol processing 128 full duplex serial PCM channels. It performs HDLC-based layer 2 protocol formatting and deformatting, as well as rate ...

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Electrical Characteristics 5.1 Important Electrical Requirements V = 3.3 V 0.3 V DD3 V = 5.0 V 0.25 V DD5 During all MUNICH128X power-up and power-down situations the difference – | may not exceed 3.6V. The ...

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Similar criteria also apply to power down in case of power failure situations: power failure: V break down U/V DD5 5V +/- 0.25V 3.3V +/- 0.3V 0. Within the grey boxes any shape of V limits of each ...

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Absolute Maximum Ratings Table 5-1 Absolute Maximum Ratings Parameter Ambient temperature under bias PEB PEF Junction temperature under bias Storage temperature Voltage at any pin with respect to ground 1) ESD robustness HBM: 1 100 pF 1) ...

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Operating Range Parameter Ambient temperature PEB PEF Supply voltage VDD3 Supply voltage VDD5 Ground Note: In the operating range, the functions given in the circuit description are fulfilled. Hardware Reference Manual Symbol Limit Values min. max ...

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DC Characteristics a) Non-PCI Interface Pins Table 5-3 Non-PCI Interface Pins Parameter Symbo l L-input voltage V V H-input voltage L-output voltage V V H-output voltage Power operational I supply I ...

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PCI Pins According to the PCI specification V2.1 from June 1, 1995 (Chapter 4: Electrical Specification for 5 V signalling) Note: According the electrical characteristics all DEMUX Interface pins (DPCI(1:0), A(27:2), W/R) are treated as PCI Interface pins. 5.6 ...

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AC Characteristics a) Non-PCI Interface Pins DD5 Inputs are driven to 2.4 V for a logical “1” and to 0.4 V for a logical “0”. Timing measurements ...

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PCI Bus Interface Timing The AC testing input/output waveforms are shown in figures 5-2 and 5-3 below Clock test val Output Delay t on TRI-STATE Output Figure 5-2 PCI Output Timing Measurement Waveforms ...

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As a master the MUNICH128X reads/writes data from/to host memory using DMA and burst. The slave mode is used by an CPU to access the MUNICH128X PCI Configuration Space and the on-chip registers. 5.7.1.1 PCI Read Transaction The transaction starts ...

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CLK 1 2 FRAME AD Address C/BE Bus CMD IRDY TRDY DEVSEL Address Phase Figure 5-4 PCI Read Transaction Hardware Reference Manual Data 1 Data 2 BE’s Data Data Phase Phase Bus Transaction 46 PEB 20324 ...

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PCI Write Transaction The transaction starts when FRAME is activated (clock 2 in figure 5-5). A write transaction is similar to a read transaction except no turnaround cycle is required following the address phase. In the example, the first ...

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PCI Timing Characteristics When the MUNICH128X operates as a PCI Master (initiator) and it either reads or writes a burst – as controlled by the on-chip DMA controller – it does not deactivate IRDY between consecutive data. In other ...

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Voltage (V) Figure 5-6 PCI Clock Specification Table 5-8 PCI Clock Characteristics Parameter CLK cycle time CLK high time CLK low time CLK slew rate (see note) Note: Rise and fall times are specified in terms of the edge rate ...

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Table 5-9 PCI Interface Signal Characteristics Parameter CLK to signal valid delay bussed signals CLK to signal valid delay point-to-point Float to active delay Active to float delay Input setup time to CLK bussed signals Input setup time to CLK ...

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De-multiplexed Bus Interface CLK FRAME D ( Address don´t care A ( W/R TRDY Figure 5-7 Master Single READ Transaction followed by a Master Single WRITE Transaction in De-multiplexed Bus Configuration ...

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Table 5-10 Additional De-multiplexed Interface Signal Characteristics Parameter CLK to address bus signal valid delay CLK to W/R signal valid delay Address bus Input setup time to CLK Address bus Input hold time to CLK W/R signal Input setup time ...

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PCM Serial Interface Timing 37 RSP RxCLK RxD 44 TSP TxCLK TxD TDTRI Figure 5-9 PCM Serial Interface Timing Hardware Reference Manual Electrical Characteristics PEB 20324 PEF ...

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Table 5-11 PCM Serial Interface Timing No. Parameter 37 Receive strobe guard time 38 Receive strobe setup 39 Receive strobe hold 40 Receive data setup 41 Receive data hold 42 Receive clock high width 43 Receive clock low width 44 ...

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System Interface Timing RES Figure 5-10 System Interface Timing Table 5-12 System Interface Timing No. Parameter 57 RESET pulse width Hardware Reference Manual Electrical Characteristics 57 ITD10332 Limit Values min. max. 4 CLK cycles 55 PEB 20324 PEF 20324 ...

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JTAG-Boundary Scan Timing TCK TMS TDI TDO Figure 5-11 JTAG-Boundary Scan Timing Table 5-13 JTAG-Boundary Scan Timing No. Parameter 58 TCK period 59 TCK high time 60 TCK low time 61 TMS setup time 62 TMS hold time 63 ...

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Test Modes 6.1 Boundary Scan Unit In the MUNICH128X a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. ...

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TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller state to another; constant ’1’ on TMS leads to normal operation of the chip. Table 6-1 Boundary Scan Sequence in MUNICH128X TDI -> Seq. Pin ...

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Seq. Pin No. 26 AD24 27 C/BE3 28 IDSEL 29 AD23 30 AD22 31 AD21 32 AD20 33 AD19 34 AD18 35 AD17 36 AD16 37 C/BE2 38 FRAME 39 IRDY 40 TRDY 41 DEVSEL 42 STOP 43 PERR 44 ...

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Seq. Pin No. 56 AD7 57 AD6 58 AD5 59 AD4 60 AD3 61 AD2 62 AD1 63 AD0 64 INTA 65 A15 66 A14 67 A13 68 A12 69 A11 70 A10 ...

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Seq. Pin No. 86 RCLK3 87 TCLK2 88 TSP2 89 TD2 90 TDEN2 91 RD2 92 RSP2 93 RCLK2 94 TCLK1 95 TSP1 96 TD1 97 TDEN1 98 RD1 99 RSP1 100 RCLK1 101 TCLK0 102 TSP0 103 TD0 104 ...

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The desired test mode is selected by serially loading a 3-bit instruction code into the instruction register via TDI (LSB first); see Table 6-2. Table 6-2 Boundary Scan Test Modes Instruction (Bit 2 … 0) 000 001 010 011 111 ...

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Package Outlines • P-MQFP-160-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Hardware Reference Manual Package Outlines Dimensions in mm ...

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