mk50x256cmb100 Freescale Semiconductor, Inc, mk50x256cmb100 Datasheet - Page 61

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mk50x256cmb100

Manufacturer Part Number
mk50x256cmb100
Description
Arm Cortex-m4 Core With Dsp
Manufacturer
Freescale Semiconductor, Inc
Datasheet
6.8.6 I
See
6.8.7 UART switching specifications
See
6.8.8 I
This section provides the AC timings for the I
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
Freescale Semiconductor, Inc.
DS11
DS12
DS13
DS14
DS15
DS16
Num
General switching
General switching
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
2
2
C switching specifications
S switching specifications
Table 45. Slave mode DSPI timing (high-speed mode) (continued)
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Figure 27. DSPI classic SPI timing — slave mode
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
specifications.
specifications.
DS13
DS15
Description
First data
First data
DS14
Preliminary
DS10
DS12
2
S in master (clocks driven) and slave
Data
Data
Peripheral operating requirements and behaviors
DS11
Min.
DS9
0
2
7
Last data
Last data
DS16
Max.
TBD
14
14
Unit
ns
ns
ns
ns
ns
ns
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