mk50x256cmb100 Freescale Semiconductor, Inc, mk50x256cmb100 Datasheet - Page 65

• Manufacturer Part Number: mk50x256cmb100
• Description: Arm Cortex-m4 Core With Dsp
• Manufacturer: Freescale Semiconductor, Inc

8.1 K50 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Freescale Semiconductor, Inc.
MAP
BGA
81
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LQF
80
10
11
12
13
14
15
16
17
18
19
P
1
2
3
4
5
6
7
8
9
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
ADC1_SE1
6/
Pin Name
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
ADC1_SE1
6/
Default
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
ADC1_SE1
6/
ALT0
ALT1
ALT2
Preliminary
NOTE
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
Pinout
65