z87001 ZiLOG Semiconductor, z87001 Datasheet
z87001
Related parts for z87001
z87001 Summary of contents
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... Z87001 in this document also apply to the Z87L01 unless specifically noted. The Z87001 is the ROMless version of the Z87000 Spread Spectrum Controller IC. Specifically intended to facilitate user specific software development, the Z87001 can ac- cess kwords of external program ROM. ...
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... Spectrum Controller Telephone Line Interface Base Station Figure 1. System Block Diagram of a Z87001/Z87010 Based Phone 2 optional microcontroller rather than by the Z87001’s DSP core. In combination with an RF section designed according to the system specifications, Zilog’s Z87010/Z87L10 ADPCM Processor, a standard 8-bit PCM telephone codec and minimal additional phone circuity, the Z87001 and its em- bedded software provide a total system solution ...
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... Transmit FSK Modulator Rate Buffer 256 Word RAM 0 Frame Counter(s), Event Trigger, DSP Core T/R Switch Ctrl, Power On/Off Ctrl, Antenna Select Figure 2. Z87001 Functional Block Diagram Z87001/Z87L01 VXDATA[7..0] VXADD[2..0] Z87010 VXSTRB Interface VXRWB VXRDYB CLKOUT CODCLK ...
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... P19 addr3 GND addr2 P18 addr1 P17 addr0 P16 idata15 VDD idata14 37 P15 4 Z87001 Figure 3. 144 Pin QFP Pin Configuration Zilog VXDATA0 109 data0 VXDATA1 data1 VXDATA2 data2 VDD VXDATA3 data3 VXDATA4 data4 VXDATA5 ...
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... External register address bus ADPCM processor read/write control trice ROMless mode select ADPCM processor address bus Clock to codec (2.048 MHz) irwb External register read/write control Master reset Interrupt enable Z87001/Z87L01 Direction 1 Output – Input – – Output Output Input/Output – ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller PIN DESCRIPTION (Continued) No Symbol 129 130 MCLK 132 triadd 133 PAON 134 dspclk 135 SYLE 137 RXSW 139 TXSW 142 PWLV 143 RSSI 6 Table 1. 144 Pin QFP Pin Configuration Function halt Halt/ single step control Master clock (16 ...
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... All voltages are referenced to GND. Positive current flows into the referenced pins. Standard test conditions are as follows: 3.0V < V < 3.6V (Z87L01) DD 4.5V < V < 5.5V (Z87001) DD GND = - DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller Stresses greater than those listed under Absolute Maxi- ...
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... OL2 I Output Low Current, ICE pins (1)) OLICE T Operating Temperature A Notes: 1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. Maximum 3 pins total from P0[15..0] and P1[15..0] 8 Table 3. 5V 0.5V Operation (Z87001) Parameter Table 4. 3.3V 0.3V Operation (Z87L01) Parameter 0.7 V GND -0 Min Max 4.5 5.5 2 ...
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... Standby Mode Current(2) CC2 Notes: 1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. Maximum 3 pins total from P0[15..0] and P1[15..0] 3. 1.6 mA typical 3.3 volts. DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller Table 5. 5V 0.5V Operation (Z87001) Test Condition V min, I max DD OH min, I max ...
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... Settling time Conversion time Aperture delay Aperture uncertainty(2) Input voltage range (p-p) Reference voltage Z87L01 Z87001 Input resistance Input capacitance Notes: Window of time while input signal is applied to sampling capacitor; see next figure. Uncertainty in sampling time due to random variations such as thermal noise. 10 Table 7. 1-Bit ADC (Temperature: -20/+70 C) ...
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... Acquisition Settling Time Time Figure 6. 1-Bit ADC Definition of Terms Minimum Typical - 3.0 3.3 4.5 5.0 0- Z87001/Z87L01 Latched Output Conversion + Time (for digital output) Maximum Units - bit 1 LSB 0.5 LSB 70 mW 120 ns 2 Msps 3 Kohm - ...
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... Power dissipation load Power dissipation load, Stop mode Conversion time (input change to output change) Rise time (full swing) Output slew rate Output voltage range Supply Range (= Z87L01 Z87001 Output load resistance Output load capacitance 12 Table 9. 4-bit DAC (Temperature: -20/+70 C) Minimum - - - - ...
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... ROMless Spread Spectrum Cordless Phone Controller , AV , GND, AGND, The RX analog input pin has an input capacitance pF. The RSSI analog input pin has an input capacitance of 10 pF. Table 10. Clocks, Reset and RF Interface Parameter Z87001/Z87L01 Min Max Units ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller ADPCM Processor Interface The Z87001 is a peripheral device for the ADPCM Proces- sor. The interface from the Z87001 perspective is com- posed of an input address bus, a bidirectional data bus, strobe and read/write input control signals and a ready/wait output control signal ...
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... CLKOUT CODCLK MCLK RESETB PAON TXSW RXSW RFEON SYLE DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller TwC(2) TrC(3) TfC(3) TpC (1) TfCC(4) TrCC(4) TfCO(5) TrCO( TwR(6) TfRF(7) TrRF(7) Figure 7. Transceiver Output Signal Z87001/Z87L01 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller VXADD VXRWB VXSTRB VXDATA VXRDYB VXADD VXRWB VXSTRB VXDATA VXRDYB 16 TsAS(8) TaDrS(10) VXDATA Read Cycle TsAS(8) TwS(12) TsDwS(13) VXDATA Write Cycle Figure 8. Read/Write Cycle TImings Zilog ThSA(9) ThDrS(11) ThSA(9) ...
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... Figure 9. Read/Write Cycle Timing with Wait StatE DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller TsAS(8) TaDrRY(15) VXDATA Read Cycle with Wait State TsAS(8) TwS(12) TsDwS(13) VXDATA Write Cycle with Wait State Z87001/Z87L01 ThSA(9) ThDrS(11) TdSRY(16) ThSA(9) ThDwS(14) TdSRY(16 ...
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... Must be driven high or not connect- ed for handset, low for base. P0[15..0] (input/output). General-purpose I/O port. Direc- tion is bit-programmable. Pins P0[3..0],when configured in input mode, can also be individually programmed as wake- up pins for the Z87001 (wake-up active low; signal internal- ly debounced and synchronized to the bit clock P1[15 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller FUNCTIONAL DESCRIPTION The functional partitioning of the Z87001 is shown in Fig- ure 2. The chip consists of a receiver, a transmitter, and several additional functional blocks.The receiver consists of the following blocks: Receive 1-bit ADC Demodulator, including: – IF Downconverter – ...
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... MHz by the 1-bit ADC, provides a 2.508 MHz useful image. The first local oscillator used to downconvert this IF signal is obtained from a Numerically Controlled Oscillator (NCO) internal to the Z87001, at the nominal frequency of 460 kHz. The resulting signal is thus at 2.048 MHz (= 2.508 MHz - 460 kHz). A second downconversion by a 2.048 MHz signal brings the receive signal to baseband ...
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... The data is sourced from the Z87010 or the Z87001 core processor. As for the receive rate buffer, the Z87010 sees a unique pipe to write to, while the Z87001 DSP core ac- cesses the rate buffer as random-access memory. The modulator reads from the rate buffer as from a circular buffer ...
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... Strength Indicator (RSSI) RSSI information is typically generated from the last stage of the RF receiver. The RSSI is sampled once per frame by the 8-bit ADC and used by the Z87001 software to com- pute the necessary Transmit Power Level voltages. DSP Core Processor A DSP core processor constitutes the heart of the Z87001. ...
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... The data interface allows the Z87010 processor direct ac- 3FFFh cess to the Z87001’s receive and transmit rate buffers. The 3FFEh rate buffers are decoded on the pin to of the Z87001, and 3FFDh dedicated voice processor interface logic handles the ad- 3FFCh dressing within the rate buffers. ...
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... The CORE_BIAS_DATA and BIAS_ERROR_DATA are two’s complement numbers in units of 125 Hz. In addition to correcting the difference in clock frequencies on the receiver using the AFC loop, a Z87001-base system can also modify the frequency of the remote transmit IF signals. The software has access to this frequency through the MOD_FREQ register fields ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) Modulator Control The MOD_FREQ fields specify the carrier center frequen- cy (should be programmed to 2.508 MHz) and deviation for the FSK signal (should be programmed to 32.58 kHz). In addition, wave shaping is performed on bit transitions, in order to satisfy FCC regulations four different inter- mediate deviation values are programmable for each of the two FSK states ...
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... Two possible 16-bit data patterns are pre-programmed in the Z87001. One is named UW (Unique Word) and is used in acquisition mode for first-time synchronization to an in- coming signal. UW can also be used to track an acquired signal ...
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... In order to detect synchronizations, the software has ac- cess to the SYNC_ACQ_IND status field. This field is set by the Z87001 matching hardware every time a match is detected within the right time window. The software must reset the “IND” bit by setting the SYNC_ACQ_CLEAR field. ...
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... A first field, RFEON_POLARITY, controls the polarity of the RFEON pin. This pin should be used to control the power of the RF module asserted by the Z87001 when the RF module is in use, and de-asserted in sleep mode. The sleep mode is used by the handset to save battery life when no phone call is in process (See “ ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) The following figure and table summarize the RF interface control fields. HBSW DSP Core Processor TX_ENABLE Table 4. Timing and RF Interface Control Fields Field RFEON_POLARITY HOP_ENABLE SYLE_POLARITY TX_ENABLE MOD_PWR_ON RFRX_PWR_ON/OFF DEMOD_PWR_ON/OFF RFRX_POLARITY RFTX_PWR_ON/OFF RFTX_POLARITY ...
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... Processor data interface. The transmit and receive rate 1 EXT6 buffers each contain 36 4-bit nibbles. To write to the transmit rate buffer, the Z87001 core pro- cessor must first set the nibble address in the TX_BUF_ADDR register field, then write the nibble data through TX_BUF_DATA. If the TX_AUTO_INCREMENT ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller OPERATION (Continued) The operation of the receive rate buffer is identical. The Z87001 core processor must set the nibble address in RX_BUF_ADDR, then read RX_BUF_DATA. If the RX_AUTO_INCREMENT bit is set, the read address is automatically incriminated (modulo 36 = number of nibbles in rate buffer) after each data read. ...
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... One input pin (RSSI) connects an external “receive signal strength indicator” half flash 8- bit ADC in the Z87001. This ADC is sampled once per frame during the receive portion of the TDD cycle. The RSSI value can be accessed in software in the RSSI_DATA register field ...
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... Zilog REGISTER DESCRIPTION The Z87001 DSP core processor has four banks of eight registers mapped in the core processor’s “external regis- ter” space, as summarized in the following table. BANK ADDRESS REGISTER Bank 3 EXT0 CONFIG1 EXT1 CONFIG2 EXT2 SSPSTATE EXT3 SSPSTATUS EXT4 GPIO0DIR ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) The bank is selectable in software by writing to the core’s status register (see Table 24). Once a bank is selected, Bank Status Register Bank 0 xxxx xxxx x00x xxxx b Bank 1 xxxx xxxx x01x xxxx b Bank 2 xxxx xxxx x10x xxxx b ...
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... SLEEP_PERIOD. In sleep mode, the RFEON pin is active. Changes to this bit take effect immediately. 2. SLEEP_REMAINING. A non-zero value indicates that the Z87001 was awakened by a key press activating one of the wake-up pins on port 0. In this case, the processor should immediately reset the SLEEP_WAKE field in SSPSTATE to prevent the pro- cess from going back to sleep when the user key press ceases ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) SSPSTATE Bank 3 Field Bit Position SW_SYLE f--------------- STOP_CODCLK -e-------------- DBP_STOP_CLOCK --d------------- BSYNC_GAIN ---c------------ BIAS_ENABLE ----b----------- TX_ENABLE -----a---------- SYNC_SEARCH_WORD ------9--------- SYNC_SEARCH_MODE -------87------- HOP_ENABLE ---------6------ SYNC_ACQ_CLEAR ----------5----- FRAME_START_CLEAR -----------4---- SLEEP_WAKE ------------3--- MULTIPLEX_SWITCH -------------21- 36 Table 14. Bank 3 Register Description EXT2 R/W Data Description Controls accelerated synthesizer programming after sleep ...
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... EXT2 R/W Data Description Command bit to place the Z87001 in sleep mode R Returns last value written W 0->1 A transition from causes Z87001 sleep mode Global enable for all transmit functions R/W 0* Transmitter disabled 1 Transmitter enabled Controls the word searched for in search mode R/W 0* Search for UW pattern (Unique Word) ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) SSPSTATUS Bank 3 Field Bit Position FRAME_COUNTER fedcba987------ RESERVED ---------65---- HAND_BASE_SEL -----------4--- SYNC_ACQ_IND ------------3-- FRAME_START_IND ------------2-- RESERVED -------------10 Notes: FRAME_COUNTER. Read the double-buffered current value of the Frame Counter. On the handset, a single frame counter is used to clock transmit and receive events. ...
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... Table 18. Bank 3 Register Description EXT6 R/W Data Independent control of Port 1 pin direction R/W ..0. Pin in input mode ..1. Pin in output mode Table 19. Bank 3 Register Description EXT7 R/W Data Access to Port 1 data R XXXXh Reads pin values W XXXXh Writes output pin values Z87001/Z87L01 Description Description Description 39 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Bank 2 Registers VP_INOUT Bank 2 Field Bit Position RESERVED fedcba98-------- VP_STATUS --------76543210 VP_COMMAND --------76543210 RX_CONTROL Bank 2 Field Bit Position SNR_ESTIMATE fedcba9876543210 UW_LOCATION -------876543210 Notes: SNR_ESTIMATE. This value is updated every frame. It should be read by the software during the frequency hopping guard time of the next frame. ...
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... Updates bias value Table 25. Bank 2 Register Description EXT5 R/W Data R Returns effect Determines modulator turn-on time referenced to the transmit frame counter R Returns 0 W xXh Bits 6-0 of turn-on time (=(x modulo 128) -1) R Returns effect Z87001/Z87L01 Description Description Description 41 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) DEMOD_PWR_CTRL Bank 2 Field Bit Position RFEON_POLARITY f--------------- DEMOD_PWR_ON -edcba98-------- RESERVED --------7------- DEMOD_PWR_OFF ---------6543210 Notes: 1. DEMOD_PWR_ON, DEMOD_PWR_OFF. Controls internal receive hardware and the RXSW output pin. The turn-on and off times are given in number of received bit periods and are referenced to the Receive Frame Counter. Only the 7 LSBits of the 9-bit value are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected. For DEMOD_PWR_ON, the two bits are “ ...
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... R Returns 0 W xXh Bits 6-0 of turn-on time (=(x modulo 128) -1) R Returns effect Determine PAON output pin turn-off time referenced to the transmit frame counter R Returns 0 W xXh Bits 6-0 of turn-off time (=(x modulo 128) - Z87001/Z87L01 Description 43 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Bank 1 Registers RATE_BUF_ADDR Bank 1 Field Bit Position RESERVED f-------------- RX_AUTO_INCREMENT -e------------- RX_BUF_ADDR --dcba98-------- RESERVED --------7------- TX_AUTO_INCREMENT ---------6------ TX_BUF_ADDR ----------543210 44 Table 28. Bank 1 Register Description EXT0 R/W Data R Returns effect Controls the auto-increment feature of the Rx rate R buffer W 0 Returns 0 1 Disables auto-increment ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller REGISTER DESCRIPTION (Continued) RATE_BUF_DATA Bank 1 Field Bit Position RX_BUF_DATA ------------3210 TX_BUF_DATA ------------3210 TX_BUF_VP_ADDR --dcba98-------- RX_BUF_VP_ADDR ----------543210 TX_RX_NIBBLE_MARKER fedcba9876543210 MOD_FREQ fedcba9876543210 Note: The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register. MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz. ...
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... TX_PWR_DAC_DATA ------------3210 Note: P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87001 sleep mode. The input signal is internally debounced and synchronized to the bit clock internally given a minimum duration of one bit to allow the software to exit sleep mode safely. ...
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... Table 35. Bank 0 Register Description EXT6 R/W Data R Returns effect Read access to the integrated symbol error from the bit synchronizer’s second order loop R XXh Reads error data bits [7..0] (bits [23..8] are in bank1, EXT2 effect Z87001/Z87L01 Description Description 47 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller RFRX_PWR_CTRL Bank 0 Field Bit Position RFRX_POLARITY f--------------- RFRX_PWR_ON -edcba98-------- RESERVED --------7------- RFRX_PWR_OFF ---------6543210 Notes: 1. RFRX_POLARITY. Caution: notice the inverse polarity of the TXSW pin. 2. RFRX_PWR_ON, RFRX_PWR_OFF. Controls the TXSW output pin. The turn-on and off times are given in number of trans- mitted bit periods and are referenced to the TRANSMIT (!) Frame Counter ...
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... CIEF None COPF None CP<src1>,<src2> A,<pregs> A,<dregs> A,<memind> A,<direct> A,<regind> A,<hwregs> A,<limm> DEC [<cc>,]<dest> <cc>A, A INC [<cc>,] <dest> <cc>, [<cc>,]<address> <cc>,<direct> <direct> Z87001/Z87L01 # # Words Cycles Example 1 1 ABS NC ABS ADD A,P0 ADD A,D0 ADD A,#%1234 1 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller Instruction Description Opcode LD Load destination with source 0000000 0000001 0001001 0000001 0000101 0000011 0000111 0000100 0001100 0001010 0000110 0000010 0001001 0000001 0000100 0100101 0000101 0000001 0000000 MLD Multiply 1010010 1010010 1011011 1011011 MPYA Multiply and add ...
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... None SRA<cc>,A <cc>,A A SUB<dest>,<src> A,<pregs> A,<dregs> A,<limm> A, <memind> A, <direct> A, <regind> A, <hwregs> XOR <dest>,<src> A, <pregs> A, <dregs> A, <limm> A, <memind> A, <direct> A, <regind> A, <hwregs> Z87001/Z87L01 # # Words Cycles Example 1 1 POP P0 POP D0 POP @P0 POP PUSH P0:0 ...