el1881 Intersil Corporation, el1881 Datasheet

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el1881

Manufacturer Part Number
el1881
Description
Sync Separator, Low Power
Manufacturer
Intersil Corporation
Datasheet

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Sync Separator, Low Power
The EL1881 video sync separator is manufactured using
Elantec’s high performance analog CMOS process. This
device extracts sync timing information from both standard
and non-standard video input. It provides composite sync,
vertical sync, burst/back porch timing, and odd/even field
detection. Fixed 70mV sync tip slicing provides sync edge
detection when the video input level is between 0.5V
-2V
external resistor sets all internal timing to adjust for various
video standards. The composite sync output follows video in
sync pulses and a vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical pre-
equalizing string. For non-standard vertical inputs, a default
vertical pulse is output when the vertical signal stays low for
longer than the vertical sync default delay time. The
odd/even output indicates field polarity detected during the
vertical blanking interval. The EL1881 is plug-in compatible
with the industry-standard LM1881 and can be substituted
for that part in 5V applications with lower required supply
current.
The EL1881 is available in the 8-pin PDIP and SO packages
and is specified for operation over the full -40°C to +85°C
temperature range.
Ordering Information
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
EL1881CN
EL1881CS
EL1881CS-T7
EL1881CS-T13
EL1881CSZ
(See Note)
EL1881CSZ-T7
(See Note)
EL1881CSZ-T13
(See Note)
PART NUMBER
P-P
(sync tip amplitude 143mV to 572mV). A single
PACKAGE
8-Pin PDIP
8-Pin SO
8-Pin SO
8-Pin SO
8-Pin SO
8-Pin SO
8-Pin SO
(Pb-free)
(Pb-free)
(Pb-free)
®
1
TAPE & REEL
Data Sheet
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
13”
13”
7”
7”
-
-
-
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
DWG. #
P-P
PKG.
1-888-INTERSIL or 321-724-7143
and
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• NTSC, PAL, SECAM, non-standard video sync separation
• Fixed 70mV slicing of video input levels from 0.5V
• Low supply current - 1.5mA typ.
• Single +5V supply
• Composite, vertical sync output
• Odd/even field output
• Burst/back porch output
• Available in 8-pin PDIP and SO packages
• Pb-free available
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High-speed communications
• RGB applications
• Broadcast equipment
• Active filtering
Demo Board
A dedicated demo board is available.
Pinout
COMPOSITE SYNC OUT
COMPOSITE VIDEO IN
2V
VERTICAL SYNC OUT
October 20, 2004
P-P
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
GND
(8-PIN PDIP, SO)
1
2
3
4
TOP VIEW
EL1881
8
7
6
5
BUST/BACK
PORCH OUTPUT
ODD/EVEN OUTPUT
V
R
DD
SET
EL1881
5V
FN7018.1
P-P
to

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el1881 Summary of contents

Page 1

... The EL1881 is plug-in compatible with the industry-standard LM1881 and can be substituted for that part in 5V applications with lower required supply current. The EL1881 is available in the 8-pin PDIP and SO packages and is specified for operation over the full -40°C to +85°C temperature range. Ordering Information ...

Page 2

... Burst/Back Porch Delay, t See Figure 2 BD Burst/Back Porch Width, t See Figure 2 B Input Dynamic Range Video Input Amplitude to Maintain 50% Slice Spec Slice Level V SLICE 2 EL1881C = 25°C) Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C +0.5V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW 5V 25° ...

Page 3

... SET 3 EL1881C Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase) Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period Supply ground Burst/back porch output ...

Page 4

... Clamp Discharge Current vs Temperature R =681kΩ SET 11.4 11.3 5.5V 11.2 11.1 4.5V 11 10.9 10.8 10.7 -50 -25 0 Temperature (°C) Clamp Charge Current vs Temperature R =681kΩ SET 1.1 1. 0.95 0.9 0.85 -50 -25 0 Temperature (°C) 4 EL1881C V CLAMP R SET 1.535 1.525 5V 1.515 1.505 1.495 1.485 100 -50 V RSET R SET 1.24 1.235 1.23 1.225 5V 1.22 1.215 1.21 1.205 1 ...

Page 5

... R SET Composite Sync Prop Delay vs Temperature -50 -25 0 Temperature (°C) 5 EL1881C (Continued) Burst/Back Porch Delay vs R SET V 350 300 250 200 150 100 50 0 600 800 1000 200 (kΩ) SET Vertical Default Delay vs R SET ...

Page 6

... Vertical Sync Default Delay Time vs Temperature R =681kΩ SET 64.5 63.5 5.5V 62.5 5V 61.5 4.5V 60.5 59.5 -50 -25 0 Temperature (°C) Composite Sync to Odd/Even Delay Time R =681kΩ SET -50 -25 0 Temperature (°C) 6 EL1881C (Continued) 239 237 5V 235 233 231 229 100 100 1.4 1.2 4. 0.8 0.6 0.4 5.5V 0.2 ...

Page 7

... Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). * Signal 1a drawing reproduced with permission from EIA. 7 EL1881C FIGURE 1. STANDARD (NTSC INPUT) TIMING FN7018.1 ...

Page 8

... Expanded Timing Diagrams 8 EL1881C FIGURE 2. STANDARD VERTICAL TIMING FIGURE 3. NON-STANDARD VERTICAL TIMING FN7018.1 ...

Page 9

... This gives a period of 63.6µs and a time T = 58.9µs. The droop voltage will then 9 EL1881C FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL 5.9mV. This is less than nominal sync tip amplitude of 286mV. The charge represented by this droop is replaced in a time given CV/I, where I = clamp charge current = 1mA ...

Page 10

... Vertical Sync is clocked out of the EL1881 on the first rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60µ ...

Page 11

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 EL1881C CLAMP SYNC TIP REF 1 ...

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