74abt833 NXP Semiconductors, 74abt833 Datasheet - Page 2

• Manufacturer Part Number: 74abt833
• Description: Octal Transceiver With Parity Generator/checker 3-state
• Manufacturer: NXP Semiconductors

FEATURES
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
Philips Semiconductors
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
2002 Dec 17
Low static and dynamic power dissipation with high speed and
high output drive
Open-collector ERROR output with flag register
Output capability: +64 mA / –32 mA
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up/down 3-State
Live insertion/extraction permitted
Octal transceiver with parity generator/checker
(3-State)
SYMBOL
I
t
t
t
t
C
C
PLH
PHL
PLH
PHL
CCZ
I/O
IN
PACKAGES
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
I/O capacitance
Total supply current
ERROR
CLEAR
OEA
GND
A0
A1
A2
A3
A4
A5
A6
A7
12
10
11
1
2
3
4
5
6
7
8
9
PARAMETER
TOP VIEW
24
23
22
20
19
18
17
16
15
14
13
21
SA00212
V
B0
B1
B2
B3
B4
B5
B6
B7
PARITY
OEB
CP
CC
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
C
C
V
Outputs disabled; V
Outputs disabled; V
L
L
I
= 0 V or V
= 50 pF; V
= 50 pF; V
2
T
CC
amb
CC
CC
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
When Output Enable A (OEA) is HIGH, it will place the A outputs in
a high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is LOW. When OEA is LOW, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
LOW-to-HIGH transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go LOW. The error flag register is cleared with a LOW
pulse on the CLEAR input.
If both OEA and OEB are LOW, data will flow from the A bus to the
B bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
PIN DESCRIPTION
= 5 V
= 5 V
CONDITIONS
= 25 C; GND = 0 V
SYMBOL
A0 – A7
B0 – B7
PARITY
ERROR
CLEAR
O
CC
OEA
OEB
GND
V
CP
= 0 V or V
CC
= 5.5 V
23, 22, 21, 20,
PIN NUMBER
19, 18, 17, 16
CC
PART NUMBER
74ABT833PW
74ABT833DB
2, 3, 4, 5,
74ABT833D
6, 7, 8, 9
14
15
10
13
12
24
11
1
A port 3-State inputs/outputs
B port 3-State inputs/outputs
Enables the A outputs when LOW
Enables the B outputs when LOW
Parity output/input
Error output (open collector)
Clears the error flag register
when LOW
Clock input
Ground (0 V)
Positive supply voltage
NAME AND FUNCTION
TYPICAL
3.4
7.4
50
4
7
74ABT833
DWG NUMBER
SOT137-1
SOT340-1
SOT355-1
Product data
UNIT
pF
pF
ns
ns
A