w9425g8eh Winbond Electronics Corp America, w9425g8eh Datasheet - Page 16

• Manufacturer Part Number: w9425g8eh
• Description: 8m ? 4 Banks ? 8 Bits Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

7.10.3 CAS Latency field (A6 to A4)
7.10.4 DLL Reset bit (A8)
7.10.5 Mode Register /Extended Mode register change bits (BS0, BS1)
7.10.6 Extended Mode Register field
7.10.7 Reserved field
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
These bits are used to select MRS/EMRS.
1) DLL Switch field (A0)
2) Output Driver Size Control field (A1)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
• Test mode entry bit (A7)
• Reserved bits (A9, A10, A11, A12)
This bit is used to select DLL enable or disable
This bit is used to select Output Driver Size, both Full strength and Half strength are based on
JEDEC standard.
A6
BS1
This bit is used to enter Test mode and must be set to "0" for normal operation.
These bits are reserved for future operations. They must be set to "0" for normal operation.
0
0
0
0
1
1
1
1
0
0
1
A0
A1
0
1
0
1
A5
0
0
1
1
0
0
1
1
BS0
0
1
x
A4
0
1
0
1
0
1
0
1
- 16 -
OUTPUT DRIVER
Half Strength
Full Strength
Extended MRS Cycle
Regular MRS Cycle
Disable
Enable
DLL
Reserved
A12-A0
Publication Release Date: Jul. 04
CAS LATENCY
Reserved
Reserved
Reserved
Reserved
Reserved
2.5
2
3
Revision A01
,
2008